mdio-mux-gpio.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
  8
  9maintainers:
 10  - Andrew Lunn <andrew@lunn.ch>
 11
 12description:
 13  This is a special case of a MDIO bus multiplexer.  One or more GPIO
 14  lines are used to control which child bus is connected.
 15
 16allOf:
 17  - $ref: /schemas/net/mdio-mux.yaml#
 18
 19properties:
 20  compatible:
 21    const: mdio-mux-gpio
 22
 23  gpios:
 24    description:
 25      List of GPIOs used to control the multiplexer, least significant bit first.
 26    minItems: 1
 27    maxItems: 32
 28
 29required:
 30  - compatible
 31  - gpios
 32
 33unevaluatedProperties: false
 34
 35examples:
 36  - |
 37    /*
 38     An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
 39     pair of GPIO lines.  Child busses 2 and 3 populated with 4
 40     PHYs each.
 41     */
 42    mdio-mux {
 43        compatible = "mdio-mux-gpio";
 44        gpios = <&gpio1 3 0>, <&gpio1 4 0>;
 45        mdio-parent-bus = <&smi1>;
 46        #address-cells = <1>;
 47        #size-cells = <0>;
 48
 49        mdio@2 {
 50            reg = <2>;
 51            #address-cells = <1>;
 52            #size-cells = <0>;
 53
 54            ethernet-phy@1 {
 55                reg = <1>;
 56                interrupt-parent = <&gpio>;
 57                interrupts = <10 8>; /* Pin 10, active low */
 58            };
 59            ethernet-phy@2 {
 60                reg = <2>;
 61                interrupt-parent = <&gpio>;
 62                interrupts = <10 8>; /* Pin 10, active low */
 63            };
 64            ethernet-phy@3 {
 65                reg = <3>;
 66                interrupt-parent = <&gpio>;
 67                interrupts = <10 8>; /* Pin 10, active low */
 68            };
 69            ethernet-phy@4 {
 70                reg = <4>;
 71                interrupt-parent = <&gpio>;
 72                interrupts = <10 8>; /* Pin 10, active low */
 73            };
 74        };
 75
 76        mdio@3 {
 77            reg = <3>;
 78            #address-cells = <1>;
 79            #size-cells = <0>;
 80
 81            ethernet-phy@1 {
 82                reg = <1>;
 83                interrupt-parent = <&gpio>;
 84                interrupts = <12 8>; /* Pin 12, active low */
 85            };
 86            ethernet-phy@2 {
 87                reg = <2>;
 88                interrupt-parent = <&gpio>;
 89                interrupts = <12 8>; /* Pin 12, active low */
 90            };
 91            ethernet-phy@3 {
 92                reg = <3>;
 93                interrupt-parent = <&gpio>;
 94                interrupts = <12 8>; /* Pin 12, active low */
 95            };
 96            ethernet-phy@4 {
 97                reg = <4>;
 98                interrupt-parent = <&gpio>;
 99                interrupts = <12 8>; /* Pin 12, active low */
100            };
101        };
102    };
103...