nxp,sja1105.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NXP SJA1105 Automotive Ethernet Switch Family
  8
  9description:
 10  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
 11  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
 12  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
 13  depends on the SPI bus master driver.
 14
 15maintainers:
 16  - Vladimir Oltean <vladimir.oltean@nxp.com>
 17
 18properties:
 19  compatible:
 20    enum:
 21      - nxp,sja1105e
 22      - nxp,sja1105t
 23      - nxp,sja1105p
 24      - nxp,sja1105q
 25      - nxp,sja1105r
 26      - nxp,sja1105s
 27      - nxp,sja1110a
 28      - nxp,sja1110b
 29      - nxp,sja1110c
 30      - nxp,sja1110d
 31
 32  reg:
 33    maxItems: 1
 34
 35  reset-gpios:
 36    description:
 37      A GPIO connected to the active-low RST_N pin of the SJA1105. Note that
 38      reset of this chip is performed via SPI and the RST_N pin must be wired
 39      to satisfy the power-up sequence documented in "SJA1105PQRS Application
 40      Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is
 41      therefore discouraged.
 42    maxItems: 1
 43
 44  clocks:
 45    maxItems: 1
 46
 47  spi-cpha: true
 48  spi-cpol: true
 49
 50  # Optional container node for the 2 internal MDIO buses of the SJA1110
 51  # (one for the internal 100base-T1 PHYs and the other for the single
 52  # 100base-TX PHY). The "reg" property does not have physical significance.
 53  # The PHY addresses to port correspondence is as follows: for 100base-T1,
 54  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
 55  # PHY 1.
 56  mdios:
 57    type: object
 58    additionalProperties: false
 59
 60    properties:
 61      '#address-cells':
 62        const: 1
 63      '#size-cells':
 64        const: 0
 65
 66    patternProperties:
 67      "^mdio@[0-1]$":
 68        $ref: /schemas/net/mdio.yaml#
 69        unevaluatedProperties: false
 70
 71        properties:
 72          compatible:
 73            oneOf:
 74              - enum:
 75                  - nxp,sja1110-base-t1-mdio
 76                  - nxp,sja1110-base-tx-mdio
 77
 78          reg:
 79            oneOf:
 80              - enum:
 81                  - 0
 82                  - 1
 83
 84        required:
 85          - compatible
 86          - reg
 87
 88patternProperties:
 89  "^(ethernet-)?ports$":
 90    additionalProperties: true
 91    patternProperties:
 92      "^(ethernet-)?port@[0-9]$":
 93        allOf:
 94          - if:
 95              properties:
 96                phy-mode:
 97                  contains:
 98                    enum:
 99                      - rgmii
100                      - rgmii-rxid
101                      - rgmii-txid
102                      - rgmii-id
103            then:
104              properties:
105                rx-internal-delay-ps:
106                  $ref: "#/$defs/internal-delay-ps"
107                tx-internal-delay-ps:
108                  $ref: "#/$defs/internal-delay-ps"
109
110required:
111  - compatible
112  - reg
113
114$defs:
115  internal-delay-ps:
116    description:
117      Disable tunable delay lines using 0 ps, or enable them and select
118      the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
119      (101.7 degree shift) in increments of 0.9 degrees (20 ps).
120    enum:
121      [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
122       1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
123       2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
124
125allOf:
126  - $ref: dsa.yaml#/$defs/ethernet-ports
127  - $ref: /schemas/spi/spi-peripheral-props.yaml#
128  - if:
129      properties:
130        compatible:
131          enum:
132            - nxp,sja1105e
133            - nxp,sja1105p
134            - nxp,sja1105q
135            - nxp,sja1105r
136            - nxp,sja1105s
137            - nxp,sja1105t
138    then:
139      properties:
140        spi-cpol: false
141      required:
142        - spi-cpha
143    else:
144      properties:
145        spi-cpha: false
146      required:
147        - spi-cpol
148
149unevaluatedProperties: false
150
151examples:
152  - |
153    spi {
154            #address-cells = <1>;
155            #size-cells = <0>;
156
157            ethernet-switch@1 {
158                    reg = <0x1>;
159                    compatible = "nxp,sja1105t";
160                    spi-cpha;
161
162                    ethernet-ports {
163                            #address-cells = <1>;
164                            #size-cells = <0>;
165
166                            port@0 {
167                                    phy-handle = <&rgmii_phy6>;
168                                    phy-mode = "rgmii-id";
169                                    rx-internal-delay-ps = <0>;
170                                    tx-internal-delay-ps = <0>;
171                                    reg = <0>;
172                            };
173
174                            port@1 {
175                                    phy-handle = <&rgmii_phy3>;
176                                    phy-mode = "rgmii-id";
177                                    rx-internal-delay-ps = <0>;
178                                    tx-internal-delay-ps = <0>;
179                                    reg = <1>;
180                            };
181
182                            port@2 {
183                                    phy-handle = <&rgmii_phy4>;
184                                    phy-mode = "rgmii-id";
185                                    rx-internal-delay-ps = <0>;
186                                    tx-internal-delay-ps = <0>;
187                                    reg = <2>;
188                            };
189
190                            port@3 {
191                                    phy-handle = <&rgmii_phy4>;
192                                    phy-mode = "rgmii-id";
193                                    rx-internal-delay-ps = <0>;
194                                    tx-internal-delay-ps = <0>;
195                                    reg = <3>;
196                            };
197
198                            port@4 {
199                                    ethernet = <&enet2>;
200                                    phy-mode = "rgmii";
201                                    rx-internal-delay-ps = <0>;
202                                    tx-internal-delay-ps = <0>;
203                                    reg = <4>;
204
205                                    fixed-link {
206                                            speed = <1000>;
207                                            full-duplex;
208                                    };
209                            };
210                    };
211            };
212    };