micrel,ks8995.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Micrel KS8995 Family DSA Switches
  8
  9maintainers:
 10  - Linus Walleij <linusw@kernel.org>
 11
 12description:
 13  The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in
 14  the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
 15  each with an internal PHY. The chip itself is managed over SPI, but all the
 16  PHYs need to be accessed from an external MDIO channel.
 17
 18  Further, a fifth PHY is available and can be used separately from the switch
 19  fabric, connected to an external MII interface name MII-P5. This is
 20  unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
 21
 22properties:
 23  compatible:
 24    enum:
 25      - micrel,ks8995
 26      - micrel,ksz8795
 27      - micrel,ksz8864
 28
 29  reg:
 30    maxItems: 1
 31
 32  reset-gpios:
 33    description: GPIO to be used to reset the whole device
 34    maxItems: 1
 35
 36allOf:
 37  - $ref: dsa.yaml#/$defs/ethernet-ports
 38  - $ref: /schemas/spi/spi-peripheral-props.yaml#
 39
 40required:
 41  - compatible
 42  - reg
 43
 44unevaluatedProperties: false
 45
 46examples:
 47  - |
 48    #include <dt-bindings/gpio/gpio.h>
 49
 50    spi {
 51      #address-cells = <1>;
 52      #size-cells = <0>;
 53
 54      ethernet-switch@0 {
 55        compatible = "micrel,ks8995";
 56        reg = <0>;
 57        spi-max-frequency = <25000000>;
 58
 59        ethernet-ports {
 60          #address-cells = <1>;
 61          #size-cells = <0>;
 62
 63          ethernet-port@0 {
 64            reg = <0>;
 65            label = "lan1";
 66          };
 67          ethernet-port@1 {
 68            reg = <1>;
 69            label = "lan2";
 70          };
 71          ethernet-port@2 {
 72            reg = <2>;
 73            label = "lan3";
 74          };
 75          ethernet-port@3 {
 76            reg = <3>;
 77            label = "lan4";
 78          };
 79          ethernet-port@4 {
 80            reg = <4>;
 81            ethernet = <&mac2>;
 82            phy-mode = "mii";
 83            fixed-link {
 84              speed = <100>;
 85              full-duplex;
 86            };
 87          };
 88        };
 89      };
 90    };
 91
 92    soc {
 93      #address-cells = <1>;
 94      #size-cells = <1>;
 95
 96      /* The WAN port connected on MII-P5 */
 97      ethernet-port@1000 {
 98        reg = <0x00001000 0x1000>;
 99        label = "wan";
100        phy-mode = "mii";
101        phy-handle = <&phy5>;
102      };
103
104      mac2: ethernet-port@2000 {
105        reg = <0x00002000 0x1000>;
106        phy-mode = "mii";
107        fixed-link {
108          speed = <100>;
109          full-duplex;
110        };
111      };
112    };
113
114    mdio {
115      #address-cells = <1>;
116      #size-cells = <0>;
117
118      /* LAN PHYs 1-4 accessible over external MDIO */
119      phy1: ethernet-phy@1 {
120        reg = <1>;
121      };
122      phy2: ethernet-phy@2 {
123        reg = <2>;
124      };
125      phy3: ethernet-phy@3 {
126        reg = <3>;
127      };
128      phy4: ethernet-phy@4 {
129        reg = <4>;
130      };
131      /* WAN PHY accessible over external MDIO */
132      phy5: ethernet-phy@5 {
133        reg = <5>;
134      };
135    };