cortina,gemini-ethernet.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Cortina Systems Gemini Ethernet Controller
  8
  9maintainers:
 10  - Linus Walleij <linusw@kernel.org>
 11
 12description: |
 13  This ethernet controller is found in the Gemini SoC family:
 14  StorLink SL3512 and SL3516, also known as Cortina Systems
 15  CS3512 and CS3516.
 16
 17properties:
 18  compatible:
 19    const: cortina,gemini-ethernet
 20
 21  reg:
 22    minItems: 3
 23    description: must contain the global registers and the V-bit and A-bit
 24      memory areas, in total three register sets.
 25
 26  "#address-cells":
 27    const: 1
 28
 29  "#size-cells":
 30    const: 1
 31
 32  ranges: true
 33
 34# The subnodes represents the two ethernet ports in this device.
 35# They are not independent of each other since they share resources
 36# in the parent node, and are thus children.
 37patternProperties:
 38  "^ethernet-port@[0-9]+$":
 39    type: object
 40    unevaluatedProperties: false
 41    description: contains the resources for ethernet port
 42    allOf:
 43      - $ref: ethernet-controller.yaml#
 44    properties:
 45      compatible:
 46        const: cortina,gemini-ethernet-port
 47
 48      reg:
 49        items:
 50          - description: DMA/TOE memory
 51          - description: GMAC memory area of the port
 52
 53      interrupts:
 54        maxItems: 1
 55        description: should contain the interrupt line of the port.
 56                     this is nominally a level interrupt active high.
 57
 58      resets:
 59        maxItems: 1
 60        description: this must provide an SoC-integrated reset line for the port.
 61
 62      clocks:
 63        maxItems: 1
 64        description: this should contain a handle to the PCLK clock for
 65                     clocking the silicon in this port
 66
 67      clock-names:
 68        const: PCLK
 69
 70    required:
 71      - reg
 72      - compatible
 73      - interrupts
 74      - resets
 75      - clocks
 76      - clock-names
 77
 78required:
 79  - compatible
 80  - reg
 81  - ranges
 82
 83additionalProperties: false
 84
 85examples:
 86  - |
 87    #include <dt-bindings/interrupt-controller/irq.h>
 88    #include <dt-bindings/clock/cortina,gemini-clock.h>
 89    #include <dt-bindings/reset/cortina,gemini-reset.h>
 90    mdio0: mdio {
 91      #address-cells = <1>;
 92      #size-cells = <0>;
 93      phy0: ethernet-phy@1 {
 94        reg = <1>;
 95        device_type = "ethernet-phy";
 96      };
 97      phy1: ethernet-phy@3 {
 98        reg = <3>;
 99        device_type = "ethernet-phy";
100      };
101    };
102
103    ethernet@60000000 {
104        compatible = "cortina,gemini-ethernet";
105        reg = <0x60000000 0x4000>, /* Global registers, queue */
106              <0x60004000 0x2000>, /* V-bit */
107              <0x60006000 0x2000>; /* A-bit */
108        #address-cells = <1>;
109        #size-cells = <1>;
110        ranges;
111
112        gmac0: ethernet-port@0 {
113                compatible = "cortina,gemini-ethernet-port";
114                reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
115                      <0x6000a000 0x2000>; /* Port 0 GMAC */
116                interrupt-parent = <&intcon>;
117                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
118                resets = <&syscon GEMINI_RESET_GMAC0>;
119                clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
120                clock-names = "PCLK";
121                phy-mode = "rgmii";
122                phy-handle = <&phy0>;
123        };
124
125        gmac1: ethernet-port@1 {
126                compatible = "cortina,gemini-ethernet-port";
127                reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
128                      <0x6000e000 0x2000>; /* Port 1 GMAC */
129                interrupt-parent = <&intcon>;
130                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
131                resets = <&syscon GEMINI_RESET_GMAC1>;
132                clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
133                clock-names = "PCLK";
134                phy-mode = "rgmii";
135                phy-handle = <&phy1>;
136        };
137    };