airoha,en7581-npu.yaml

 1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/net/airoha,en7581-npu.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Airoha Network Processor Unit for EN7581 SoC
 8
 9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11
12description:
13  The Airoha Network Processor Unit (NPU) provides a configuration interface
14  to implement wired and wireless hardware flow offloading programming Packet
15  Processor Engine (PPE) flow table.
16
17properties:
18  compatible:
19    enum:
20      - airoha,en7581-npu
21      - airoha,an7583-npu
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    items:
28      - description: mbox host irq line
29      - description: watchdog0 irq line
30      - description: watchdog1 irq line
31      - description: watchdog2 irq line
32      - description: watchdog3 irq line
33      - description: watchdog4 irq line
34      - description: watchdog5 irq line
35      - description: watchdog6 irq line
36      - description: watchdog7 irq line
37      - description: wlan irq line0
38      - description: wlan irq line1
39      - description: wlan irq line2
40      - description: wlan irq line3
41      - description: wlan irq line4
42      - description: wlan irq line5
43
44  memory-region:
45    oneOf:
46      - items:
47          - description: NPU firmware binary region
48      - items:
49          - description: NPU firmware binary region
50          - description: NPU wlan offload RX buffers region
51          - description: NPU wlan offload TX buffers region
52          - description: NPU wlan offload TX packet identifiers region
53
54  memory-region-names:
55    items:
56      - const: firmware
57      - const: pkt
58      - const: tx-pkt
59      - const: tx-bufid
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - memory-region
66
67additionalProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/interrupt-controller/irq.h>
73    soc {
74      #address-cells = <2>;
75      #size-cells = <2>;
76
77      npu@1e900000 {
78        compatible = "airoha,en7581-npu";
79        reg = <0 0x1e900000 0 0x313000>;
80        interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
81                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
82                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
83                     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
84                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
85                     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
86                     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
87                     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
88                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
89                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
90                     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
91                     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
92                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
93                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
94                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
95        memory-region = <&npu_firmware>, <&npu_pkt>, <&npu_txpkt>,
96                        <&npu_txbufid>;
97        memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid";
98      };
99    };