ti,davinci-nand.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: TI DaVinci NAND controller
  8
  9maintainers:
 10  - Marcus Folkesson <marcus.folkesson@gmail.com>
 11
 12allOf:
 13  - $ref: nand-controller.yaml
 14
 15properties:
 16  compatible:
 17    enum:
 18      - ti,davinci-nand
 19      - ti,keystone-nand
 20
 21  reg:
 22    items:
 23      - description: Access window.
 24      - description: AEMIF control registers.
 25
 26  partitions:
 27    $ref: /schemas/mtd/partitions/partitions.yaml
 28
 29  ti,davinci-chipselect:
 30    description:
 31      Number of chipselect. Indicate on the davinci_nand driver which
 32      chipselect is used for accessing the nand.
 33    $ref: /schemas/types.yaml#/definitions/uint32
 34    enum: [0, 1, 2, 3]
 35
 36  ti,davinci-mask-ale:
 37    description:
 38      Mask for ALE. Needed for executing address phase. These offset will be
 39      added to the base address for the chip select space the NAND Flash
 40      device is connected to.
 41    $ref: /schemas/types.yaml#/definitions/uint32
 42    default: 0x08
 43
 44  ti,davinci-mask-cle:
 45    description:
 46      Mask for CLE. Needed for executing command phase. These offset will be
 47      added to the base address for the chip select space the NAND Flash device
 48      is connected to.
 49    $ref: /schemas/types.yaml#/definitions/uint32
 50    default: 0x10
 51
 52  ti,davinci-mask-chipsel:
 53    description:
 54      Mask for chipselect address. Needed to mask addresses for given
 55      chipselect.
 56    $ref: /schemas/types.yaml#/definitions/uint32
 57    default: 0
 58
 59  ti,davinci-ecc-bits:
 60    description: Used ECC bits.
 61    enum: [1, 4]
 62
 63  ti,davinci-ecc-mode:
 64    description: Operation mode of the NAND ECC mode.
 65    $ref: /schemas/types.yaml#/definitions/string
 66    enum: [none, soft, hw, on-die]
 67    deprecated: true
 68
 69  ti,davinci-nand-buswidth:
 70    description: Bus width to the NAND chip.
 71    $ref: /schemas/types.yaml#/definitions/uint32
 72    enum: [8, 16]
 73    default: 8
 74    deprecated: true
 75
 76  ti,davinci-nand-use-bbt:
 77    type: boolean
 78    description:
 79      Use flash based bad block table support. OOB identifier is saved in OOB
 80      area.
 81    deprecated: true
 82
 83required:
 84  - compatible
 85  - reg
 86  - ti,davinci-chipselect
 87
 88unevaluatedProperties: false
 89
 90examples:
 91  - |
 92    bus {
 93      #address-cells = <2>;
 94      #size-cells = <1>;
 95
 96      nand-controller@2000000,0 {
 97        compatible = "ti,davinci-nand";
 98        #address-cells = <1>;
 99        #size-cells = <0>;
100        reg = <0 0x02000000 0x02000000>,
101              <1 0x00000000 0x00008000>;
102
103        ti,davinci-chipselect = <1>;
104        ti,davinci-mask-ale = <0>;
105        ti,davinci-mask-cle = <0>;
106        ti,davinci-mask-chipsel = <0>;
107
108        ti,davinci-nand-buswidth = <16>;
109        ti,davinci-ecc-mode = "hw";
110        ti,davinci-ecc-bits = <4>;
111        ti,davinci-nand-use-bbt;
112
113        partitions {
114          compatible = "fixed-partitions";
115          #address-cells = <1>;
116          #size-cells = <1>;
117
118          partition@0 {
119            label = "u-boot env";
120            reg = <0 0x020000>;
121          };
122        };
123      };
124    };