sdhci-am654.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: TI AM654 MMC Controller
  9
 10maintainers:
 11  - Ulf Hansson <ulf.hansson@linaro.org>
 12
 13allOf:
 14  - $ref: sdhci-common.yaml#
 15
 16properties:
 17  compatible:
 18    oneOf:
 19      - enum:
 20          - ti,am62-sdhci
 21          - ti,am64-sdhci-4bit
 22          - ti,am64-sdhci-8bit
 23          - ti,am654-sdhci-5.1
 24          - ti,j721e-sdhci-4bit
 25          - ti,j721e-sdhci-8bit
 26      - items:
 27          - const: ti,j7200-sdhci-8bit
 28          - const: ti,j721e-sdhci-8bit
 29      - items:
 30          - const: ti,j7200-sdhci-4bit
 31          - const: ti,j721e-sdhci-4bit
 32
 33  reg:
 34    maxItems: 2
 35
 36  interrupts:
 37    maxItems: 1
 38
 39  power-domains:
 40    maxItems: 1
 41
 42  clocks:
 43    minItems: 1
 44    maxItems: 2
 45    description: Handles to input clocks
 46
 47  clock-names:
 48    minItems: 1
 49    items:
 50      - const: clk_ahb
 51      - const: clk_xin
 52
 53  dma-coherent: true
 54
 55  # PHY output tap delays:
 56  # Used to delay the data valid window and align it to the sampling clock.
 57  # Binding needs to be provided for each supported speed mode otherwise the
 58  # corresponding mode will be disabled.
 59
 60  ti,otap-del-sel-legacy:
 61    description: Output tap delay for SD/MMC legacy timing
 62    $ref: /schemas/types.yaml#/definitions/uint32
 63    minimum: 0
 64    maximum: 0xf
 65
 66  ti,otap-del-sel-mmc-hs:
 67    description: Output tap delay for MMC high speed timing
 68    $ref: /schemas/types.yaml#/definitions/uint32
 69    minimum: 0
 70    maximum: 0xf
 71
 72  ti,otap-del-sel-sd-hs:
 73    description: Output tap delay for SD high speed timing
 74    $ref: /schemas/types.yaml#/definitions/uint32
 75    minimum: 0
 76    maximum: 0xf
 77
 78  ti,otap-del-sel-sdr12:
 79    description: Output tap delay for SD UHS SDR12 timing
 80    $ref: /schemas/types.yaml#/definitions/uint32
 81    minimum: 0
 82    maximum: 0xf
 83
 84  ti,otap-del-sel-sdr25:
 85    description: Output tap delay for SD UHS SDR25 timing
 86    $ref: /schemas/types.yaml#/definitions/uint32
 87    minimum: 0
 88    maximum: 0xf
 89
 90  ti,otap-del-sel-sdr50:
 91    description: Output tap delay for SD UHS SDR50 timing
 92    $ref: /schemas/types.yaml#/definitions/uint32
 93    minimum: 0
 94    maximum: 0xf
 95
 96  ti,otap-del-sel-sdr104:
 97    description: Output tap delay for SD UHS SDR104 timing
 98    $ref: /schemas/types.yaml#/definitions/uint32
 99    minimum: 0
100    maximum: 0xf
101
102  ti,otap-del-sel-ddr50:
103    description: Output tap delay for SD UHS DDR50 timing
104    $ref: /schemas/types.yaml#/definitions/uint32
105    minimum: 0
106    maximum: 0xf
107
108  ti,otap-del-sel-ddr52:
109    description: Output tap delay for eMMC DDR52 timing
110    $ref: /schemas/types.yaml#/definitions/uint32
111    minimum: 0
112    maximum: 0xf
113
114  ti,otap-del-sel-hs200:
115    description: Output tap delay for eMMC HS200 timing
116    $ref: /schemas/types.yaml#/definitions/uint32
117    minimum: 0
118    maximum: 0xf
119
120  ti,otap-del-sel-hs400:
121    description: Output tap delay for eMMC HS400 timing
122    $ref: /schemas/types.yaml#/definitions/uint32
123    minimum: 0
124    maximum: 0xf
125
126  # PHY input tap delays:
127  # Used to delay the data valid window and align it to the sampling clock for
128  # modes that don't support tuning
129
130  ti,itap-del-sel-legacy:
131    description: Input tap delay for SD/MMC legacy timing
132    $ref: /schemas/types.yaml#/definitions/uint32
133    minimum: 0
134    maximum: 0x1f
135
136  ti,itap-del-sel-mmc-hs:
137    description: Input tap delay for MMC high speed timing
138    $ref: /schemas/types.yaml#/definitions/uint32
139    minimum: 0
140    maximum: 0x1f
141
142  ti,itap-del-sel-sd-hs:
143    description: Input tap delay for SD high speed timing
144    $ref: /schemas/types.yaml#/definitions/uint32
145    minimum: 0
146    maximum: 0x1f
147
148  ti,itap-del-sel-sdr12:
149    description: Input tap delay for SD UHS SDR12 timing
150    $ref: /schemas/types.yaml#/definitions/uint32
151    minimum: 0
152    maximum: 0x1f
153
154  ti,itap-del-sel-sdr25:
155    description: Input tap delay for SD UHS SDR25 timing
156    $ref: /schemas/types.yaml#/definitions/uint32
157    minimum: 0
158    maximum: 0x1f
159
160  ti,itap-del-sel-ddr50:
161    description: Input tap delay for MMC DDR50 timing
162    $ref: /schemas/types.yaml#/definitions/uint32
163    minimum: 0
164    maximum: 0x1f
165
166  ti,itap-del-sel-ddr52:
167    description: Input tap delay for MMC DDR52 timing
168    $ref: /schemas/types.yaml#/definitions/uint32
169    minimum: 0
170    maximum: 0x1f
171
172  ti,trm-icp:
173    description: DLL trim select
174    $ref: /schemas/types.yaml#/definitions/uint32
175    minimum: 0
176    maximum: 0xf
177
178  ti,driver-strength-ohm:
179    description: DLL drive strength in ohms
180    $ref: /schemas/types.yaml#/definitions/uint32
181    enum:
182      - 33
183      - 40
184      - 50
185      - 66
186      - 100
187
188  ti,strobe-sel:
189    description: strobe select delay for HS400 speed mode.
190    $ref: /schemas/types.yaml#/definitions/uint32
191
192  ti,clkbuf-sel:
193    description: Clock Delay Buffer Select
194    $ref: /schemas/types.yaml#/definitions/uint32
195
196  ti,fails-without-test-cd:
197    $ref: /schemas/types.yaml#/definitions/flag
198    description:
199      When present, indicates that the CD line is not connected
200      and the controller is required to be forced into Test mode
201      to set the TESTCD bit.
202
203required:
204  - compatible
205  - reg
206  - interrupts
207  - clocks
208  - clock-names
209  - ti,otap-del-sel-legacy
210
211unevaluatedProperties: false
212
213examples:
214  - |
215    #include <dt-bindings/interrupt-controller/irq.h>
216    #include <dt-bindings/interrupt-controller/arm-gic.h>
217
218    bus {
219        #address-cells = <2>;
220        #size-cells = <2>;
221
222        mmc0: mmc@4f80000 {
223            compatible = "ti,am654-sdhci-5.1";
224            reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
225            power-domains = <&k3_pds 47>;
226            clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
227            clock-names = "clk_ahb", "clk_xin";
228            interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
229            sdhci-caps-mask = <0x80000007 0x0>;
230            mmc-ddr-1_8v;
231            ti,otap-del-sel-legacy = <0x0>;
232            ti,otap-del-sel-mmc-hs = <0x0>;
233            ti,otap-del-sel-ddr52 = <0x5>;
234            ti,otap-del-sel-hs200 = <0x5>;
235            ti,otap-del-sel-hs400 = <0x0>;
236            ti,itap-del-sel-legacy = <0x10>;
237            ti,itap-del-sel-mmc-hs = <0xa>;
238            ti,itap-del-sel-ddr52 = <0x3>;
239            ti,trm-icp = <0x8>;
240        };
241    };