samsung,exynos-dw-mshc.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title:
  8  Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
  9  Storage Host Controller
 10
 11maintainers:
 12  - Jaehoon Chung <jh80.chung@samsung.com>
 13  - Krzysztof Kozlowski <krzk@kernel.org>
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - enum:
 19          - axis,artpec8-dw-mshc
 20          - samsung,exynos4210-dw-mshc
 21          - samsung,exynos4412-dw-mshc
 22          - samsung,exynos5250-dw-mshc
 23          - samsung,exynos5420-dw-mshc
 24          - samsung,exynos5420-dw-mshc-smu
 25          - samsung,exynos7-dw-mshc
 26          - samsung,exynos7-dw-mshc-smu
 27          - samsung,exynos7870-dw-mshc
 28          - samsung,exynos7870-dw-mshc-smu
 29      - items:
 30          - enum:
 31              - samsung,exynos5433-dw-mshc-smu
 32              - samsung,exynos7885-dw-mshc-smu
 33              - samsung,exynos850-dw-mshc-smu
 34              - samsung,exynos8890-dw-mshc-smu
 35              - samsung,exynos8895-dw-mshc-smu
 36          - const: samsung,exynos7-dw-mshc-smu
 37
 38  reg:
 39    maxItems: 1
 40
 41  interrupts:
 42    maxItems: 1
 43
 44  clocks:
 45    maxItems: 2
 46    description:
 47      Handle to "biu" and "ciu" clocks for the
 48      bus interface unit clock and the card interface unit clock.
 49
 50  clock-names:
 51    items:
 52      - const: biu
 53      - const: ciu
 54
 55  samsung,dw-mshc-ciu-div:
 56    $ref: /schemas/types.yaml#/definitions/uint32
 57    minimum: 0
 58    maximum: 7
 59    description:
 60      The divider value for the card interface unit (ciu) clock.
 61
 62  samsung,dw-mshc-ddr-timing:
 63    $ref: /schemas/types.yaml#/definitions/uint32-array
 64    items:
 65      - description: CIU clock phase shift value for tx mode
 66        minimum: 0
 67        maximum: 7
 68      - description: CIU clock phase shift value for rx mode
 69        minimum: 0
 70        maximum: 7
 71    description:
 72      The value of CUI clock phase shift value in transmit mode and CIU clock
 73      phase shift value in receive mode for double data rate mode operation.
 74      See also samsung,dw-mshc-hs400-timing property.
 75
 76  samsung,dw-mshc-hs400-timing:
 77    $ref: /schemas/types.yaml#/definitions/uint32-array
 78    items:
 79      - description: CIU clock phase shift value for tx mode
 80        minimum: 0
 81        maximum: 7
 82      - description: CIU clock phase shift value for rx mode
 83        minimum: 0
 84        maximum: 7
 85    description: |
 86      The value of CIU TX and RX clock phase shift value for HS400 mode
 87      operation.
 88      Valid values for SDR and DDR CIU clock timing::
 89        - valid value for tx phase shift and rx phase shift is 0 to 7.
 90        - when CIU clock divider value is set to 3, all possible 8 phase shift
 91          values can be used.
 92        - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
 93          phase shift clocks should be 0.
 94      If missing, values from samsung,dw-mshc-ddr-timing property are used.
 95
 96  samsung,dw-mshc-sdr-timing:
 97    $ref: /schemas/types.yaml#/definitions/uint32-array
 98    items:
 99      - description: CIU clock phase shift value for tx mode
100        minimum: 0
101        maximum: 7
102      - description: CIU clock phase shift value for rx mode
103        minimum: 0
104        maximum: 7
105    description:
106      The value of CIU clock phase shift value in transmit mode and CIU clock
107      phase shift value in receive mode for single data rate mode operation.
108      See also samsung,dw-mshc-hs400-timing property.
109
110  samsung,read-strobe-delay:
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description:
113      RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
114      line in Read path). If missing, default from hardware is used.
115
116required:
117  - compatible
118  - reg
119  - interrupts
120  - clocks
121  - clock-names
122  - samsung,dw-mshc-ddr-timing
123  - samsung,dw-mshc-sdr-timing
124
125allOf:
126  - $ref: synopsys-dw-mshc-common.yaml#
127  - if:
128      properties:
129        compatible:
130          contains:
131            enum:
132              - samsung,exynos5250-dw-mshc
133              - samsung,exynos5420-dw-mshc
134              - samsung,exynos7-dw-mshc
135              - samsung,exynos7-dw-mshc-smu
136              - axis,artpec8-dw-mshc
137    then:
138      required:
139        - samsung,dw-mshc-ciu-div
140
141unevaluatedProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/clock/exynos5420.h>
146    #include <dt-bindings/interrupt-controller/arm-gic.h>
147
148    mmc@12220000 {
149        compatible = "samsung,exynos5420-dw-mshc";
150        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
151        #address-cells = <1>;
152        #size-cells = <0>;
153        reg = <0x12220000 0x1000>;
154        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
155        clock-names = "biu", "ciu";
156        fifo-depth = <0x40>;
157        card-detect-delay = <200>;
158        samsung,dw-mshc-ciu-div = <3>;
159        samsung,dw-mshc-sdr-timing = <0 4>;
160        samsung,dw-mshc-ddr-timing = <0 2>;
161        pinctrl-names = "default";
162        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
163        bus-width = <4>;
164        cap-sd-highspeed;
165        max-frequency = <200000000>;
166        vmmc-supply = <&ldo19_reg>;
167        vqmmc-supply = <&ldo13_reg>;
168        sd-uhs-sdr50;
169        sd-uhs-sdr104;
170        sd-uhs-ddr50;
171    };