cdns,sdhci.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
  8
  9maintainers:
 10  - Masahiro Yamada <yamada.masahiro@socionext.com>
 11
 12properties:
 13  compatible:
 14    items:
 15      - enum:
 16          - amd,pensando-elba-sd4hc
 17          - microchip,mpfs-sd4hc
 18          - microchip,pic64gx-sd4hc
 19          - mobileye,eyeq-sd4hc
 20          - socionext,uniphier-sd4hc
 21      - const: cdns,sd4hc
 22
 23  reg:
 24    minItems: 1
 25    maxItems: 2
 26
 27  interrupts:
 28    maxItems: 1
 29
 30  clocks:
 31    maxItems: 1
 32
 33  resets:
 34    maxItems: 1
 35
 36  # PHY DLL input delays:
 37  # They are used to delay the data valid window, and align the window to
 38  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
 39  # and it is increased by 2.5ns in each step.
 40
 41  cdns,phy-input-delay-sd-highspeed:
 42    description: Value of the delay in the input path for SD high-speed timing
 43    $ref: /schemas/types.yaml#/definitions/uint32
 44    minimum: 0
 45    maximum: 0x1f
 46
 47  cdns,phy-input-delay-legacy:
 48    description: Value of the delay in the input path for legacy timing
 49    $ref: /schemas/types.yaml#/definitions/uint32
 50    minimum: 0
 51    maximum: 0x1f
 52
 53  cdns,phy-input-delay-sd-uhs-sdr12:
 54    description: Value of the delay in the input path for SD UHS SDR12 timing
 55    $ref: /schemas/types.yaml#/definitions/uint32
 56    minimum: 0
 57    maximum: 0x1f
 58
 59  cdns,phy-input-delay-sd-uhs-sdr25:
 60    description: Value of the delay in the input path for SD UHS SDR25 timing
 61    $ref: /schemas/types.yaml#/definitions/uint32
 62    minimum: 0
 63    maximum: 0x1f
 64
 65  cdns,phy-input-delay-sd-uhs-sdr50:
 66    description: Value of the delay in the input path for SD UHS SDR50 timing
 67    $ref: /schemas/types.yaml#/definitions/uint32
 68    minimum: 0
 69    maximum: 0x1f
 70
 71  cdns,phy-input-delay-sd-uhs-ddr50:
 72    description: Value of the delay in the input path for SD UHS DDR50 timing
 73    $ref: /schemas/types.yaml#/definitions/uint32
 74    minimum: 0
 75    maximum: 0x1f
 76
 77  cdns,phy-input-delay-mmc-highspeed:
 78    description: Value of the delay in the input path for MMC high-speed timing
 79    $ref: /schemas/types.yaml#/definitions/uint32
 80    minimum: 0
 81    maximum: 0x1f
 82
 83  cdns,phy-input-delay-mmc-ddr:
 84    description: Value of the delay in the input path for eMMC high-speed DDR timing
 85
 86  # PHY DLL clock delays:
 87  # Each delay property represents the fraction of the clock period.
 88  # The approximate delay value will be
 89  # (<delay property value>/128)*sdmclk_clock_period.
 90    $ref: /schemas/types.yaml#/definitions/uint32
 91    minimum: 0
 92    maximum: 0x1f
 93
 94  cdns,phy-dll-delay-sdclk:
 95    description: |
 96      Value of the delay introduced on the sdclk output for all modes except
 97      HS200, HS400 and HS400_ES.
 98    $ref: /schemas/types.yaml#/definitions/uint32
 99    minimum: 0
100    maximum: 0x7f
101
102  cdns,phy-dll-delay-sdclk-hsmmc:
103    description: |
104      Value of the delay introduced on the sdclk output for HS200, HS400 and
105      HS400_ES speed modes.
106    $ref: /schemas/types.yaml#/definitions/uint32
107    minimum: 0
108    maximum: 0x7f
109
110  cdns,phy-dll-delay-strobe:
111    description: |
112      Value of the delay introduced on the dat_strobe input used in
113      HS400 / HS400_ES speed modes.
114    $ref: /schemas/types.yaml#/definitions/uint32
115    minimum: 0
116    maximum: 0x7f
117
118required:
119  - compatible
120  - reg
121  - interrupts
122  - clocks
123
124allOf:
125  - $ref: sdhci-common.yaml
126  - if:
127      properties:
128        compatible:
129          contains:
130            const: amd,pensando-elba-sd4hc
131    then:
132      properties:
133        reg:
134          items:
135            - description: Host controller registers
136            - description: Elba byte-lane enable register for writes
137      required:
138        - resets
139    else:
140      properties:
141        reg:
142          maxItems: 1
143
144unevaluatedProperties: false
145
146examples:
147  - |
148    emmc: mmc@5a000000 {
149        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
150        reg = <0x5a000000 0x400>;
151        interrupts = <0 78 4>;
152        clocks = <&clk 4>;
153        bus-width = <8>;
154        mmc-ddr-1_8v;
155        mmc-hs200-1_8v;
156        mmc-hs400-1_8v;
157        cdns,phy-dll-delay-sdclk = <0>;
158    };