xlnx,sd-fec.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Xilinx SDFEC(16nm) IP
  8
  9maintainers:
 10  - Cvetic, Dragan <dragan.cvetic@amd.com>
 11  - Erim, Salih <salih.erim@amd.com>
 12
 13description:
 14  The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
 15  which provides high-throughput LDPC and Turbo Code implementations.
 16  The LDPC decode & encode functionality is capable of covering a range of
 17  customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
 18  principally covers codes used by LTE. The FEC Engine offers significant
 19  power and area savings versus implementations done in the FPGA fabric.
 20
 21properties:
 22  compatible:
 23    const: xlnx,sd-fec-1.1
 24
 25  reg:
 26    maxItems: 1
 27
 28  clocks:
 29    minItems: 2
 30    maxItems: 8
 31    additionalItems: true
 32    items:
 33      - description: Main processing clock for processing core
 34      - description: AXI4-Lite memory-mapped slave interface clock
 35      - description: Control input AXI4-Stream Slave interface clock
 36      - description: DIN AXI4-Stream Slave interface clock
 37      - description: Status output AXI4-Stream Master interface clock
 38      - description: DOUT AXI4-Stream Master interface clock
 39      - description: DIN_WORDS AXI4-Stream Slave interface clock
 40      - description: DOUT_WORDS AXI4-Stream Master interface clock
 41
 42  clock-names:
 43    allOf:
 44      - minItems: 2
 45        maxItems: 8
 46        additionalItems: true
 47        items:
 48          - const: core_clk
 49          - const: s_axi_aclk
 50      - items:
 51          enum:
 52            - core_clk
 53            - s_axi_aclk
 54            - s_axis_ctrl_aclk
 55            - s_axis_din_aclk
 56            - m_axis_status_aclk
 57            - m_axis_dout_aclk
 58            - s_axis_din_words_aclk
 59            - m_axis_dout_words_aclk
 60
 61  interrupts:
 62    maxItems: 1
 63
 64  xlnx,sdfec-code:
 65    description:
 66      The SD-FEC integrated block supports Low Density Parity Check (LDPC)
 67      decoding and encoding and Turbo code decoding. The LDPC codes used are
 68      highly configurable, and the specific code used can be specified on
 69      a codeword-by-codeword basis. The Turbo code decoding is required by LTE
 70      standard.
 71    $ref: /schemas/types.yaml#/definitions/string
 72    items:
 73      enum: [ ldpc, turbo ]
 74
 75  xlnx,sdfec-din-width:
 76    description:
 77      Configures the DIN AXI stream where a value of 1
 78      configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
 79      of "4x128b".
 80    $ref: /schemas/types.yaml#/definitions/uint32
 81    enum: [ 1, 2, 4 ]
 82
 83  xlnx,sdfec-din-words:
 84    description:
 85      A value 0 indicates that the DIN_WORDS interface is
 86      driven with a fixed value and is not present on the device, a value of 1
 87      configures the DIN_WORDS to be block based, while a value of 2 configures the
 88      DIN_WORDS input to be supplied for each AXI transaction.
 89    $ref: /schemas/types.yaml#/definitions/uint32
 90    enum: [ 0, 1, 2 ]
 91
 92  xlnx,sdfec-dout-width:
 93    description:
 94      Configures the DOUT AXI stream where a value of 1 configures a width of "1x128b",
 95      2 a width of "2x128b" and 4 configures a width of "4x128b".
 96    $ref: /schemas/types.yaml#/definitions/uint32
 97    enum: [ 1, 2, 4 ]
 98
 99  xlnx,sdfec-dout-words:
100    description:
101      A value 0 indicates that the DOUT_WORDS interface is
102      driven with a fixed value and is not present on the device, a value of 1
103      configures the DOUT_WORDS to be block based, while a value of 2 configures the
104      DOUT_WORDS input to be supplied for each AXI transaction.
105    $ref: /schemas/types.yaml#/definitions/uint32
106    enum: [ 0, 1, 2 ]
107
108required:
109  - compatible
110  - reg
111  - clocks
112  - clock-names
113  - xlnx,sdfec-code
114  - xlnx,sdfec-din-width
115  - xlnx,sdfec-din-words
116  - xlnx,sdfec-dout-width
117  - xlnx,sdfec-dout-words
118
119additionalProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/interrupt-controller/irq.h>
124
125    sd-fec@a0040000 {
126        compatible = "xlnx,sd-fec-1.1";
127        reg = <0xa0040000 0x40000>;
128        clocks = <&misc_clk_2>, <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_1>,
129                 <&misc_clk_1>, <&misc_clk_1>;
130        clock-names = "core_clk", "s_axi_aclk", "s_axis_ctrl_aclk",
131                      "s_axis_din_aclk", "m_axis_status_aclk",
132                      "m_axis_dout_aclk";
133        interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
134        xlnx,sdfec-code = "ldpc";
135        xlnx,sdfec-din-width = <2>;
136        xlnx,sdfec-din-words = <0>;
137        xlnx,sdfec-dout-width = <1>;
138        xlnx,sdfec-dout-words = <0>;
139    };
140