nxp,lpc1850-creg.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mfd/nxp,lpc1850-creg.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: The NXP LPC18xx/43xx CREG (Configuration Registers) block
  8
  9maintainers:
 10  - Frank Li <Frank.Li@nxp.com>
 11
 12properties:
 13  compatible:
 14    items:
 15      - enum:
 16          - nxp,lpc1850-creg
 17      - const: syscon
 18      - const: simple-mfd
 19
 20  reg:
 21    maxItems: 1
 22
 23  clocks:
 24    maxItems: 1
 25
 26  resets:
 27    maxItems: 1
 28
 29  clock-controller:
 30    type: object
 31    description:
 32      The NXP LPC18xx/43xx CREG (Configuration Registers) block contains
 33      control registers for two low speed clocks. One of the clocks is a
 34      32 kHz oscillator driver with power up/down and clock gating. Next
 35      is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
 36
 37      These clocks are used by the RTC and the Event Router peripherals.
 38      The 32 kHz can also be routed to other peripherals to enable low
 39      power modes.
 40
 41    properties:
 42      compatible:
 43        const: nxp,lpc1850-creg-clk
 44
 45      clocks:
 46        maxItems: 1
 47
 48      '#clock-cells':
 49        const: 1
 50        description: |
 51          0            1 kHz clock
 52          1           32 kHz Oscillator
 53
 54    required:
 55      - compatible
 56      - clocks
 57      - '#clock-cells'
 58
 59    additionalProperties: false
 60
 61  phy:
 62    type: object
 63    description: the internal USB OTG PHY in NXP LPC18xx and LPC43xx SoCs
 64    properties:
 65      compatible:
 66        const: nxp,lpc1850-usb-otg-phy
 67
 68      clocks:
 69        maxItems: 1
 70
 71      '#phy-cells':
 72        const: 0
 73
 74    required:
 75      - compatible
 76      - clocks
 77      - '#phy-cells'
 78
 79    additionalProperties: false
 80
 81  dma-mux:
 82    type: object
 83    description: NXP LPC18xx/43xx DMA MUX (DMA request router)
 84    properties:
 85      compatible:
 86        const: nxp,lpc1850-dmamux
 87
 88      '#dma-cells':
 89        const: 3
 90        description: |
 91          Should be set to <3>.
 92          * 1st cell contain the master dma request signal
 93          * 2nd cell contain the mux value (0-3) for the peripheral
 94          * 3rd cell contain either 1 or 2 depending on the AHB  master used.
 95
 96      dma-requests:
 97        $ref: /schemas/types.yaml#/definitions/uint32
 98        maximum: 64
 99        description: Number of DMA requests the controller can handle
100
101      dma-masters:
102        $ref: /schemas/types.yaml#/definitions/phandle
103        description: phandle pointing to the DMA controller
104
105    required:
106      - compatible
107      - '#dma-cells'
108      - dma-masters
109
110    additionalProperties: false
111
112required:
113  - compatible
114  - reg
115  - clocks
116  - resets
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/clock/lpc18xx-ccu.h>
123
124    syscon@40043000 {
125        compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
126        reg = <0x40043000 0x1000>;
127        clocks = <&ccu1 CLK_CPU_CREG>;
128        resets = <&rgu 5>;
129
130        clock-controller {
131            compatible = "nxp,lpc1850-creg-clk";
132            clocks = <&xtal32>;
133            #clock-cells = <1>;
134        };
135
136        phy {
137            compatible = "nxp,lpc1850-usb-otg-phy";
138            clocks = <&ccu1 CLK_USB0>;
139            #phy-cells = <0>;
140        };
141
142        dma-mux {
143            compatible = "nxp,lpc1850-dmamux";
144            #dma-cells = <3>;
145            dma-requests = <64>;
146            dma-masters = <&dmac>;
147        };
148    };