mscc,ocelot.yaml

  1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Ocelot Externally-Controlled Ethernet Switch
  8
  9maintainers:
 10  - Colin Foster <colin.foster@in-advantage.com>
 11
 12description: |
 13  The Ocelot ethernet switch family contains chips that have an internal CPU
 14  (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have
 15  the option to be controlled externally via external interfaces like SPI or
 16  PCIe.
 17
 18  The switch family is a multi-port networking switch that supports many
 19  interfaces. Additionally, the device can perform pin control, MDIO buses, and
 20  external GPIO expanders.
 21
 22properties:
 23  compatible:
 24    enum:
 25      - mscc,vsc7512
 26
 27  reg:
 28    maxItems: 1
 29
 30  "#address-cells":
 31    const: 1
 32
 33  "#size-cells":
 34    const: 1
 35
 36  spi-max-frequency:
 37    maxItems: 1
 38
 39patternProperties:
 40  "^pinctrl@[0-9a-f]+$":
 41    type: object
 42    $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
 43
 44  "^gpio@[0-9a-f]+$":
 45    type: object
 46    $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
 47    properties:
 48      compatible:
 49        enum:
 50          - mscc,ocelot-sgpio
 51
 52  "^mdio@[0-9a-f]+$":
 53    type: object
 54    $ref: /schemas/net/mscc,miim.yaml
 55    properties:
 56      compatible:
 57        enum:
 58          - mscc,ocelot-miim
 59
 60  "^ethernet-switch@[0-9a-f]+$":
 61    type: object
 62    $ref: /schemas/net/mscc,vsc7514-switch.yaml
 63    unevaluatedProperties: false
 64    properties:
 65      compatible:
 66        enum:
 67          - mscc,vsc7512-switch
 68
 69required:
 70  - compatible
 71  - reg
 72  - '#address-cells'
 73  - '#size-cells'
 74
 75additionalProperties: false
 76
 77examples:
 78  - |
 79    spi {
 80        #address-cells = <1>;
 81        #size-cells = <0>;
 82
 83        soc@0 {
 84            compatible = "mscc,vsc7512";
 85            spi-max-frequency = <2500000>;
 86            reg = <0>;
 87            #address-cells = <1>;
 88            #size-cells = <1>;
 89
 90            mdio@7107009c {
 91                compatible = "mscc,ocelot-miim";
 92                #address-cells = <1>;
 93                #size-cells = <0>;
 94                reg = <0x7107009c 0x24>;
 95
 96                sw_phy0: ethernet-phy@0 {
 97                    reg = <0x0>;
 98                };
 99            };
100
101            mdio@710700c0 {
102                compatible = "mscc,ocelot-miim";
103                pinctrl-names = "default";
104                pinctrl-0 = <&miim1_pins>;
105                #address-cells = <1>;
106                #size-cells = <0>;
107                reg = <0x710700c0 0x24>;
108
109                sw_phy4: ethernet-phy@4 {
110                    reg = <0x4>;
111                };
112            };
113
114            gpio: pinctrl@71070034 {
115                compatible = "mscc,ocelot-pinctrl";
116                gpio-controller;
117                #gpio-cells = <2>;
118                gpio-ranges = <&gpio 0 0 22>;
119                reg = <0x71070034 0x6c>;
120
121                sgpio_pins: sgpio-pins {
122                    pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
123                    function = "sg0";
124                };
125
126                miim1_pins: miim1-pins {
127                    pins = "GPIO_14", "GPIO_15";
128                    function = "miim";
129                };
130            };
131
132            gpio@710700f8 {
133                compatible = "mscc,ocelot-sgpio";
134                #address-cells = <1>;
135                #size-cells = <0>;
136                bus-frequency = <12500000>;
137                clocks = <&ocelot_clock>;
138                microchip,sgpio-port-ranges = <0 15>;
139                pinctrl-names = "default";
140                pinctrl-0 = <&sgpio_pins>;
141                reg = <0x710700f8 0x100>;
142
143                sgpio_in0: gpio@0 {
144                    compatible = "microchip,sparx5-sgpio-bank";
145                    reg = <0>;
146                    gpio-controller;
147                    #gpio-cells = <3>;
148                    ngpios = <64>;
149                };
150
151                sgpio_out1: gpio@1 {
152                    compatible = "microchip,sparx5-sgpio-bank";
153                    reg = <1>;
154                    gpio-controller;
155                    #gpio-cells = <3>;
156                    ngpios = <64>;
157                };
158            };
159        };
160    };
161
162...
163