aspeed,ast2x00-scu.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Aspeed System Control Unit
  8
  9description:
 10  The Aspeed System Control Unit manages the global behaviour of the SoC,
 11  configuring elements such as clocks, pinmux, and reset.
 12  In AST2700 SOC which has two soc connection, each soc have its own scu
 13  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
 14
 15maintainers:
 16  - Joel Stanley <joel@jms.id.au>
 17  - Andrew Jeffery <andrew@aj.id.au>
 18
 19properties:
 20  compatible:
 21    items:
 22      - enum:
 23          - aspeed,ast2400-scu
 24          - aspeed,ast2500-scu
 25          - aspeed,ast2600-scu
 26          - aspeed,ast2700-scu0
 27          - aspeed,ast2700-scu1
 28      - const: syscon
 29      - const: simple-mfd
 30
 31  reg:
 32    maxItems: 1
 33
 34  ranges: true
 35
 36  '#address-cells':
 37    minimum: 1
 38    maximum: 2
 39
 40  '#size-cells':
 41    const: 1
 42
 43  '#clock-cells':
 44    const: 1
 45
 46  '#reset-cells':
 47    const: 1
 48
 49patternProperties:
 50  '^p2a-control@[0-9a-f]+$':
 51    description: >
 52      PCI-to-AHB Bridge Control
 53
 54      The bridge is available on platforms with the VGA enabled on the Aspeed
 55      device. In this case, the host has access to a 64KiB window into all of
 56      the BMC's memory. The BMC can disable this bridge. If the bridge is
 57      enabled, the host has read access to all the regions of memory, however
 58      the host only has read and write access depending on a register
 59      controlled by the BMC.
 60    type: object
 61    additionalProperties: false
 62
 63    properties:
 64      compatible:
 65        enum:
 66          - aspeed,ast2400-p2a-ctrl
 67          - aspeed,ast2500-p2a-ctrl
 68      reg:
 69        maxItems: 1
 70
 71      memory-region:
 72        maxItems: 1
 73        description:
 74          A reserved_memory region to be used for the PCI to AHB mapping
 75
 76    required:
 77      - compatible
 78      - reg
 79
 80  '^pinctrl(@[0-9a-f]+)?$':
 81    type: object
 82    additionalProperties: true
 83    properties:
 84      compatible:
 85        contains:
 86          enum:
 87            - aspeed,ast2400-pinctrl
 88            - aspeed,ast2500-pinctrl
 89            - aspeed,ast2600-pinctrl
 90
 91    required:
 92      - compatible
 93
 94  '^interrupt-controller@[0-9a-f]+$':
 95    type: object
 96    additionalProperties: true
 97    properties:
 98      compatible:
 99        contains:
100          enum:
101            - aspeed,ast2500-scu-ic
102            - aspeed,ast2600-scu-ic0
103            - aspeed,ast2600-scu-ic1
104            - aspeed,ast2700-scu-ic0
105            - aspeed,ast2700-scu-ic1
106            - aspeed,ast2700-scu-ic2
107            - aspeed,ast2700-scu-ic3
108
109  '^silicon-id@[0-9a-f]+$':
110    description: Unique hardware silicon identifiers within the SoC
111    type: object
112    additionalProperties: false
113
114    properties:
115      compatible:
116        items:
117          - enum:
118              - aspeed,ast2400-silicon-id
119              - aspeed,ast2500-silicon-id
120              - aspeed,ast2600-silicon-id
121              - aspeed,ast2700-silicon-id
122          - const: aspeed,silicon-id
123
124      reg:
125        description:
126          The reg should be the unique silicon id register, and not backwards
127          compatible one in eg. the 2600.
128        minItems: 1
129        items:
130          - description: silicon id information registers
131          - description: unique chip id registers
132
133required:
134  - compatible
135  - reg
136  - ranges
137  - '#address-cells'
138  - '#size-cells'
139  - '#clock-cells'
140  - '#reset-cells'
141
142additionalProperties: false
143
144examples:
145  - |
146    syscon@1e6e2000 {
147        compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
148        reg = <0x1e6e2000 0x1a8>;
149        #clock-cells = <1>;
150        #reset-cells = <1>;
151
152        #address-cells = <1>;
153        #size-cells = <1>;
154        ranges = <0x0 0x1e6e2000 0x1000>;
155
156        p2a-control@2c {
157            compatible = "aspeed,ast2400-p2a-ctrl";
158            reg = <0x2c 0x4>;
159        };
160
161        silicon-id@7c {
162            compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
163            reg = <0x7c 0x4>, <0x150 0x8>;
164        };
165    };
166...