st,stm32-fmc2-ebi-props.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Peripheral properties for ST FMC2 Controller
  8
  9maintainers:
 10  - Christophe Kerello <christophe.kerello@foss.st.com>
 11  - Marek Vasut <marex@denx.de>
 12
 13properties:
 14  st,fmc2-ebi-cs-transaction-type:
 15    description: |
 16      Select one of the transactions type supported
 17      0: Asynchronous mode 1 SRAM/FRAM.
 18      1: Asynchronous mode 1 PSRAM.
 19      2: Asynchronous mode A SRAM/FRAM.
 20      3: Asynchronous mode A PSRAM.
 21      4: Asynchronous mode 2 NOR.
 22      5: Asynchronous mode B NOR.
 23      6: Asynchronous mode C NOR.
 24      7: Asynchronous mode D NOR.
 25      8: Synchronous read synchronous write PSRAM.
 26      9: Synchronous read asynchronous write PSRAM.
 27      10: Synchronous read synchronous write NOR.
 28      11: Synchronous read asynchronous write NOR.
 29    $ref: /schemas/types.yaml#/definitions/uint32
 30    minimum: 0
 31    maximum: 11
 32
 33  st,fmc2-ebi-cs-cclk-enable:
 34    description: Continuous clock enable (first bank must be configured
 35      in synchronous mode). The FMC_CLK is generated continuously
 36      during asynchronous and synchronous access. By default, the
 37      FMC_CLK is only generated during synchronous access.
 38    $ref: /schemas/types.yaml#/definitions/flag
 39
 40  st,fmc2-ebi-cs-mux-enable:
 41    description: Address/Data multiplexed on databus (valid only with
 42      NOR and PSRAM transactions type). By default, Address/Data
 43      are not multiplexed.
 44    $ref: /schemas/types.yaml#/definitions/flag
 45
 46  st,fmc2-ebi-cs-buswidth:
 47    description: Data bus width
 48    $ref: /schemas/types.yaml#/definitions/uint32
 49    enum: [ 8, 16 ]
 50    default: 16
 51
 52  st,fmc2-ebi-cs-waitpol-high:
 53    description: Wait signal polarity (NWAIT signal active high).
 54      By default, NWAIT is active low.
 55    $ref: /schemas/types.yaml#/definitions/flag
 56
 57  st,fmc2-ebi-cs-waitcfg-enable:
 58    description: The NWAIT signal indicates wheither the data from the
 59      device are valid or if a wait state must be inserted when accessing
 60      the device in synchronous mode. By default, the NWAIT signal is
 61      active one data cycle before wait state.
 62    $ref: /schemas/types.yaml#/definitions/flag
 63
 64  st,fmc2-ebi-cs-wait-enable:
 65    description: The NWAIT signal is enabled (its level is taken into
 66      account after the programmed latency period to insert wait states
 67      if asserted). By default, the NWAIT signal is disabled.
 68    $ref: /schemas/types.yaml#/definitions/flag
 69
 70  st,fmc2-ebi-cs-asyncwait-enable:
 71    description: The NWAIT signal is taken into account during asynchronous
 72      transactions. By default, the NWAIT signal is not taken into account
 73      during asynchronous transactions.
 74    $ref: /schemas/types.yaml#/definitions/flag
 75
 76  st,fmc2-ebi-cs-cpsize:
 77    description: CRAM page size. The controller splits the burst access
 78      when the memory page is reached. By default, no burst split when
 79      crossing page boundary.
 80    $ref: /schemas/types.yaml#/definitions/uint32
 81    enum: [ 0, 128, 256, 512, 1024 ]
 82    default: 0
 83
 84  st,fmc2-ebi-cs-byte-lane-setup-ns:
 85    description: This property configures the byte lane setup timing
 86      defined in nanoseconds from NBLx low to Chip Select NEx low.
 87
 88  st,fmc2-ebi-cs-address-setup-ns:
 89    description: This property defines the duration of the address setup
 90      phase in nanoseconds used for asynchronous read/write transactions.
 91
 92  st,fmc2-ebi-cs-address-hold-ns:
 93    description: This property defines the duration of the address hold
 94      phase in nanoseconds used for asynchronous multiplexed read/write
 95      transactions.
 96
 97  st,fmc2-ebi-cs-data-setup-ns:
 98    description: This property defines the duration of the data setup phase
 99      in nanoseconds used for asynchronous read/write transactions.
100
101  st,fmc2-ebi-cs-bus-turnaround-ns:
102    description: This property defines the delay in nanoseconds between the
103      end of current read/write transaction and the next transaction.
104
105  st,fmc2-ebi-cs-data-hold-ns:
106    description: This property defines the duration of the data hold phase
107      in nanoseconds used for asynchronous read/write transactions.
108
109  st,fmc2-ebi-cs-clk-period-ns:
110    description: This property defines the FMC_CLK output signal period in
111      nanoseconds.
112
113  st,fmc2-ebi-cs-data-latency-ns:
114    description: This property defines the data latency before reading or
115      writing the first data in nanoseconds.
116
117  st,fmc2-ebi-cs-write-address-setup-ns:
118    description: This property defines the duration of the address setup
119      phase in nanoseconds used for asynchronous write transactions.
120
121  st,fmc2-ebi-cs-write-address-hold-ns:
122    description: This property defines the duration of the address hold
123      phase in nanoseconds used for asynchronous multiplexed write
124      transactions.
125
126  st,fmc2-ebi-cs-write-data-setup-ns:
127    description: This property defines the duration of the data setup
128      phase in nanoseconds used for asynchronous write transactions.
129
130  st,fmc2-ebi-cs-write-bus-turnaround-ns:
131    description: This property defines the delay between the end of current
132      write transaction and the next transaction in nanoseconds.
133
134  st,fmc2-ebi-cs-write-data-hold-ns:
135    description: This property defines the duration of the data hold phase
136      in nanoseconds used for asynchronous write transactions.
137
138  st,fmc2-ebi-cs-max-low-pulse-ns:
139    description: This property defines the maximum chip select low pulse
140      duration in nanoseconds for synchronous transactions. When this timing
141      reaches 0, the controller splits the current access, toggles NE to
142      allow device refresh and restarts a new access.
143
144additionalProperties: true