renesas,rzg3e-xspi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas Expanded Serial Peripheral Interface (xSPI)
  8
  9maintainers:
 10  - Biju Das <biju.das.jz@bp.renesas.com>
 11
 12description: |
 13  Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
 14  the memory-mapping or the manual command mode.
 15
 16  The flash chip itself should be represented by a subnode of the XSPI node.
 17  The flash interface is selected based on the "compatible" property of this
 18  subnode:
 19  -  "jedec,spi-nor";
 20
 21allOf:
 22  - $ref: /schemas/spi/spi-controller.yaml#
 23
 24properties:
 25  compatible:
 26    oneOf:
 27      - const: renesas,r9a09g047-xspi  # RZ/G3E
 28
 29      - items:
 30          - enum:
 31              - renesas,r9a09g056-xspi  # RZ/V2N
 32              - renesas,r9a09g057-xspi  # RZ/V2H(P)
 33          - const: renesas,r9a09g047-xspi
 34
 35  reg:
 36    items:
 37      - description: xSPI registers
 38      - description: direct mapping area
 39
 40  reg-names:
 41    items:
 42      - const: regs
 43      - const: dirmap
 44
 45  interrupts:
 46    items:
 47      - description: Interrupt pulse signal by factors excluding errors
 48      - description: Interrupt pulse signal by error factors
 49
 50  interrupt-names:
 51    items:
 52      - const: pulse
 53      - const: err_pulse
 54
 55  clocks:
 56    items:
 57      - description: AHB clock
 58      - description: AXI clock
 59      - description: SPI clock
 60      - description: Double speed SPI clock
 61
 62  clock-names:
 63    items:
 64      - const: ahb
 65      - const: axi
 66      - const: spi
 67      - const: spix2
 68
 69  power-domains:
 70    maxItems: 1
 71
 72  resets:
 73    items:
 74      - description: Hardware reset
 75      - description: AXI reset
 76
 77  reset-names:
 78    items:
 79      - const: hresetn
 80      - const: aresetn
 81
 82  renesas,xspi-cs-addr-sys:
 83    $ref: /schemas/types.yaml#/definitions/phandle
 84    description: |
 85      Phandle to the system controller (sys) that allows to configure
 86      xSPI CS0 and CS1 addresses.
 87
 88patternProperties:
 89  "flash@[0-9a-f]+$":
 90    type: object
 91    additionalProperties: true
 92
 93    properties:
 94      compatible:
 95        contains:
 96          const: jedec,spi-nor
 97
 98required:
 99  - compatible
100  - reg
101  - reg-names
102  - interrupts
103  - interrupt-names
104  - clocks
105  - clock-names
106  - power-domains
107  - resets
108  - reset-names
109  - '#address-cells'
110  - '#size-cells'
111
112unevaluatedProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/interrupt-controller/arm-gic.h>
117    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
118
119    spi@11030000 {
120        compatible = "renesas,r9a09g047-xspi";
121        reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
122        reg-names = "regs", "dirmap";
123        interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
124                     <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
125        interrupt-names = "pulse", "err_pulse";
126        clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
127                 <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>;
128        clock-names = "ahb", "axi", "spi", "spix2";
129        power-domains = <&cpg>;
130        resets = <&cpg 0xa3>, <&cpg 0xa4>;
131        reset-names = "hresetn", "aresetn";
132        #address-cells = <1>;
133        #size-cells = <0>;
134
135        flash@0 {
136          compatible = "jedec,spi-nor";
137          reg = <0>;
138          spi-max-frequency = <40000000>;
139          spi-tx-bus-width = <1>;
140          spi-rx-bus-width = <1>;
141        };
142    };