jedec,lpddr2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
  8
  9maintainers:
 10  - Krzysztof Kozlowski <krzk@kernel.org>
 11
 12allOf:
 13  - $ref: jedec,lpddr-props.yaml#
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - items:
 19          - enum:
 20              - elpida,ECB240ABACN
 21              - elpida,B8132B2PB-6D-F
 22          - enum:
 23              - jedec,lpddr2-nvm
 24              - jedec,lpddr2-s2
 25              - jedec,lpddr2-s4
 26      - items:
 27          - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
 28          - enum:
 29              - jedec,lpddr2-nvm
 30              - jedec,lpddr2-s2
 31              - jedec,lpddr2-s4
 32
 33  revision-id1:
 34    $ref: /schemas/types.yaml#/definitions/uint32
 35    maximum: 255
 36    description: |
 37      Revision 1 value of SDRAM chip. Obtained from device datasheet.
 38      Property is deprecated, use revision-id instead.
 39    deprecated: true
 40
 41  revision-id2:
 42    $ref: /schemas/types.yaml#/definitions/uint32
 43    maximum: 255
 44    description: |
 45      Revision 2 value of SDRAM chip. Obtained from device datasheet.
 46      Property is deprecated, use revision-id instead.
 47    deprecated: true
 48
 49  tRRD-min-tck:
 50    $ref: /schemas/types.yaml#/definitions/uint32
 51    maximum: 16
 52    description: |
 53      Active bank a to active bank b in terms of number of clock cycles.
 54      Obtained from device datasheet.
 55
 56  tWTR-min-tck:
 57    $ref: /schemas/types.yaml#/definitions/uint32
 58    maximum: 16
 59    description: |
 60      Internal WRITE-to-READ command delay in terms of number of clock cycles.
 61      Obtained from device datasheet.
 62
 63  tXP-min-tck:
 64    $ref: /schemas/types.yaml#/definitions/uint32
 65    maximum: 16
 66    description: |
 67      Exit power-down to next valid command delay in terms of number of clock
 68      cycles. Obtained from device datasheet.
 69
 70  tRTP-min-tck:
 71    $ref: /schemas/types.yaml#/definitions/uint32
 72    maximum: 16
 73    description: |
 74      Internal READ to PRECHARGE command delay in terms of number of clock
 75      cycles. Obtained from device datasheet.
 76
 77  tCKE-min-tck:
 78    $ref: /schemas/types.yaml#/definitions/uint32
 79    maximum: 16
 80    description: |
 81      CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
 82      of clock cycles. Obtained from device datasheet.
 83
 84  tRPab-min-tck:
 85    $ref: /schemas/types.yaml#/definitions/uint32
 86    maximum: 16
 87    description: |
 88      Row precharge time (all banks) in terms of number of clock cycles.
 89      Obtained from device datasheet.
 90
 91  tRCD-min-tck:
 92    $ref: /schemas/types.yaml#/definitions/uint32
 93    maximum: 16
 94    description: |
 95      RAS-to-CAS delay in terms of number of clock cycles. Obtained from
 96      device datasheet.
 97
 98  tWR-min-tck:
 99    $ref: /schemas/types.yaml#/definitions/uint32
100    maximum: 16
101    description: |
102      WRITE recovery time in terms of number of clock cycles. Obtained from
103      device datasheet.
104
105  tRASmin-min-tck:
106    $ref: /schemas/types.yaml#/definitions/uint32
107    maximum: 16
108    description: |
109      Row active time in terms of number of clock cycles. Obtained from device
110      datasheet.
111
112  tCKESR-min-tck:
113    $ref: /schemas/types.yaml#/definitions/uint32
114    maximum: 16
115    description: |
116      CKE minimum pulse width during SELF REFRESH (low pulse width during
117      SELF REFRESH) in terms of number of clock cycles. Obtained from device
118      datasheet.
119
120  tFAW-min-tck:
121    $ref: /schemas/types.yaml#/definitions/uint32
122    maximum: 16
123    description: |
124      Four-bank activate window in terms of number of clock cycles. Obtained
125      from device datasheet.
126
127patternProperties:
128  "^lpddr2-timings":
129    $ref: jedec,lpddr2-timings.yaml
130    description: |
131      The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
132      "lpddr2-timings" provides AC timing parameters of the device for
133      a given speed-bin. The user may provide the timings for as many
134      speed-bins as is required.
135
136required:
137  - compatible
138  - density
139  - io-width
140
141unevaluatedProperties: false
142
143examples:
144  - |
145    elpida_ECB240ABACN: lpddr2 {
146        compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
147        density = <2048>;
148        io-width = <32>;
149        revision-id = <1 0>;
150
151        tRPab-min-tck = <3>;
152        tRCD-min-tck = <3>;
153        tWR-min-tck = <3>;
154        tRASmin-min-tck = <3>;
155        tRRD-min-tck = <2>;
156        tWTR-min-tck = <2>;
157        tXP-min-tck = <2>;
158        tRTP-min-tck = <2>;
159        tCKE-min-tck = <3>;
160        tCKESR-min-tck = <3>;
161        tFAW-min-tck = <8>;
162
163        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
164            compatible = "jedec,lpddr2-timings";
165            min-freq = <10000000>;
166            max-freq = <400000000>;
167            tRPab = <21000>;
168            tRCD = <18000>;
169            tWR = <15000>;
170            tRAS-min = <42000>;
171            tRRD = <10000>;
172            tWTR = <7500>;
173            tXP = <7500>;
174            tRTP = <7500>;
175            tCKESR = <15000>;
176            tDQSCK-max = <5500>;
177            tFAW = <50000>;
178            tZQCS = <90000>;
179            tZQCL = <360000>;
180            tZQinit = <1000000>;
181            tRAS-max-ns = <70000>;
182        };
183
184        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
185            compatible = "jedec,lpddr2-timings";
186            min-freq = <10000000>;
187            max-freq = <200000000>;
188            tRPab = <21000>;
189            tRCD = <18000>;
190            tWR = <15000>;
191            tRAS-min = <42000>;
192            tRRD = <10000>;
193            tWTR = <10000>;
194            tXP = <7500>;
195            tRTP = <7500>;
196            tCKESR = <15000>;
197            tDQSCK-max = <5500>;
198            tFAW = <50000>;
199            tZQCS = <90000>;
200            tZQCL = <360000>;
201            tZQinit = <1000000>;
202            tRAS-max-ns = <70000>;
203        };
204    };