snps,dw-hdmi-rx.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Device Tree bindings for Synopsys DesignWare HDMI RX Controller
  3
  4---
  5$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Synopsys DesignWare HDMI RX Controller
  9
 10maintainers:
 11  - Dmitry Osipenko <dmitry.osipenko@collabora.com>
 12
 13description:
 14  Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs
 15  allowing devices to receive and decode high-resolution video streams
 16  from external sources like media players, cameras, laptops, etc.
 17
 18properties:
 19  compatible:
 20    items:
 21      - const: rockchip,rk3588-hdmirx-ctrler
 22      - const: snps,dw-hdmi-rx
 23
 24  reg:
 25    maxItems: 1
 26
 27  interrupts:
 28    maxItems: 3
 29
 30  interrupt-names:
 31    items:
 32      - const: cec
 33      - const: hdmi
 34      - const: dma
 35
 36  clocks:
 37    maxItems: 7
 38
 39  clock-names:
 40    items:
 41      - const: aclk
 42      - const: audio
 43      - const: cr_para
 44      - const: pclk
 45      - const: ref
 46      - const: hclk_s_hdmirx
 47      - const: hclk_vo1
 48
 49  power-domains:
 50    maxItems: 1
 51
 52  resets:
 53    maxItems: 4
 54
 55  reset-names:
 56    items:
 57      - const: axi
 58      - const: apb
 59      - const: ref
 60      - const: biu
 61
 62  memory-region:
 63    maxItems: 1
 64
 65  hpd-gpios:
 66    description: GPIO specifier for HPD.
 67    maxItems: 1
 68
 69  rockchip,grf:
 70    $ref: /schemas/types.yaml#/definitions/phandle
 71    description:
 72      The phandle of the syscon node for the general register file
 73      containing HDMIRX PHY status bits.
 74
 75  rockchip,vo1-grf:
 76    $ref: /schemas/types.yaml#/definitions/phandle
 77    description:
 78      The phandle of the syscon node for the Video Output GRF register
 79      to enable EDID transfer through SDAIN and SCLIN.
 80
 81required:
 82  - compatible
 83  - reg
 84  - interrupts
 85  - interrupt-names
 86  - clocks
 87  - clock-names
 88  - power-domains
 89  - resets
 90  - pinctrl-0
 91  - hpd-gpios
 92
 93additionalProperties: false
 94
 95examples:
 96  - |
 97    #include <dt-bindings/clock/rockchip,rk3588-cru.h>
 98    #include <dt-bindings/gpio/gpio.h>
 99    #include <dt-bindings/interrupt-controller/arm-gic.h>
100    #include <dt-bindings/interrupt-controller/irq.h>
101    #include <dt-bindings/power/rk3588-power.h>
102    #include <dt-bindings/reset/rockchip,rk3588-cru.h>
103    hdmi_receiver: hdmi-receiver@fdee0000 {
104      compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
105      reg = <0xfdee0000 0x6000>;
106      interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
107                   <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
108                   <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
109      interrupt-names = "cec", "hdmi", "dma";
110      clocks = <&cru ACLK_HDMIRX>,
111               <&cru CLK_HDMIRX_AUD>,
112               <&cru CLK_CR_PARA>,
113               <&cru PCLK_HDMIRX>,
114               <&cru CLK_HDMIRX_REF>,
115               <&cru PCLK_S_HDMIRX>,
116               <&cru HCLK_VO1>;
117      clock-names = "aclk",
118                    "audio",
119                    "cr_para",
120                    "pclk",
121                    "ref",
122                    "hclk_s_hdmirx",
123                    "hclk_vo1";
124      power-domains = <&power RK3588_PD_VO1>;
125      resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
126               <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
127      reset-names = "axi", "apb", "ref", "biu";
128      memory-region = <&hdmi_receiver_cma>;
129      pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>;
130      pinctrl-names = "default";
131      hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
132    };