renesas,rzg2l-csi2.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2# Copyright (C) 2022 Renesas Electronics Corp.
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/media/renesas,rzg2l-csi2.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
  9
 10maintainers:
 11  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 12
 13description:
 14  The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
 15  (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
 16  with the Image Processing module, which provides the video capture capabilities.
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - items:
 22          - enum:
 23              - renesas,r9a07g043-csi2 # RZ/G2UL
 24              - renesas,r9a07g044-csi2 # RZ/G2{L,LC}
 25              - renesas,r9a07g054-csi2 # RZ/V2L
 26          - const: renesas,rzg2l-csi2
 27      - items:
 28          - const: renesas,r9a09g047-csi2 # RZ/G3E
 29          - const: renesas,r9a09g057-csi2
 30      - const: renesas,r9a09g057-csi2 # RZ/V2H(P)
 31
 32  reg:
 33    maxItems: 1
 34
 35  interrupts:
 36    maxItems: 1
 37
 38  clocks:
 39    oneOf:
 40      - items:
 41          - description: Internal clock for connecting CRU and MIPI
 42          - description: CRU Main clock
 43          - description: CRU Register access clock
 44      - items:
 45          - description: CRU Main clock
 46          - description: CRU Register access clock
 47
 48  clock-names:
 49    oneOf:
 50      - items:
 51          - const: system
 52          - const: video
 53          - const: apb
 54      - items:
 55          - const: video
 56          - const: apb
 57
 58  power-domains:
 59    maxItems: 1
 60
 61  resets:
 62    items:
 63      - description: CRU_PRESETN reset terminal
 64      - description: D-PHY reset (CRU_CMN_RSTB or CRU_n_S_RESETN)
 65
 66  reset-names:
 67    items:
 68      - const: presetn
 69      - const: cmn-rstb
 70
 71  ports:
 72    $ref: /schemas/graph.yaml#/properties/ports
 73
 74    properties:
 75      port@0:
 76        $ref: /schemas/graph.yaml#/$defs/port-base
 77        unevaluatedProperties: false
 78        description:
 79          Input port node, single endpoint describing the CSI-2 transmitter.
 80
 81        properties:
 82          endpoint:
 83            $ref: video-interfaces.yaml#
 84            unevaluatedProperties: false
 85
 86            properties:
 87              data-lanes:
 88                minItems: 1
 89                maxItems: 4
 90                items:
 91                  maximum: 4
 92
 93            required:
 94              - clock-lanes
 95              - data-lanes
 96
 97      port@1:
 98        $ref: /schemas/graph.yaml#/properties/port
 99        description:
100          Output port node, Image Processing block connected to the CSI-2 receiver.
101
102    required:
103      - port@0
104      - port@1
105
106required:
107  - compatible
108  - reg
109  - interrupts
110  - clocks
111  - clock-names
112  - power-domains
113  - resets
114  - reset-names
115  - ports
116
117allOf:
118  - if:
119      properties:
120        compatible:
121          contains:
122            const: renesas,r9a09g057-csi2
123    then:
124      properties:
125        clocks:
126          maxItems: 2
127        clock-names:
128          maxItems: 2
129    else:
130      properties:
131        clocks:
132          minItems: 3
133        clock-names:
134          minItems: 3
135
136additionalProperties: false
137
138examples:
139  - |
140    #include <dt-bindings/clock/r9a07g044-cpg.h>
141    #include <dt-bindings/interrupt-controller/arm-gic.h>
142
143    csi: csi@10830400 {
144        compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
145        reg = <0x10830400 0xfc00>;
146        interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
147        clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
148                 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
149                 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
150        clock-names = "system", "video", "apb";
151        power-domains = <&cpg>;
152        resets = <&cpg R9A07G044_CRU_PRESETN>,
153                 <&cpg R9A07G044_CRU_CMN_RSTB>;
154        reset-names = "presetn", "cmn-rstb";
155
156        ports {
157            #address-cells = <1>;
158            #size-cells = <0>;
159
160            port@0 {
161                reg = <0>;
162
163                csi2_in: endpoint {
164                    clock-lanes = <0>;
165                    data-lanes = <1 2>;
166                    remote-endpoint = <&ov5645_ep>;
167                };
168            };
169
170            port@1 {
171                #address-cells = <1>;
172                #size-cells = <0>;
173
174                reg = <1>;
175
176                csi2cru: endpoint@0 {
177                    reg = <0>;
178                    remote-endpoint = <&crucsi2>;
179                };
180            };
181        };
182    };