qcom,sm8750-iris.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm SM8750 SoC Iris video encoder and decoder
  8
  9maintainers:
 10  - Krzysztof Kozlowski <krzk@kernel.org>
 11
 12description:
 13  The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and
 14  decode accelerator.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - qcom,sm8750-iris
 20
 21  clocks:
 22    maxItems: 6
 23
 24  clock-names:
 25    items:
 26      - const: iface          # AXI0
 27      - const: core
 28      - const: vcodec0_core
 29      - const: iface1         # AXI1
 30      - const: core_freerun
 31      - const: vcodec0_core_freerun
 32
 33  dma-coherent: true
 34
 35  interconnects:
 36    maxItems: 2
 37
 38  interconnect-names:
 39    items:
 40      - const: cpu-cfg
 41      - const: video-mem
 42
 43  iommus:
 44    maxItems: 2
 45
 46  operating-points-v2: true
 47  opp-table:
 48    type: object
 49
 50  power-domains:
 51    maxItems: 4
 52
 53  power-domain-names:
 54    items:
 55      - const: venus
 56      - const: vcodec0
 57      - const: mxc
 58      - const: mmcx
 59
 60  resets:
 61    maxItems: 4
 62
 63  reset-names:
 64    items:
 65      - const: bus0
 66      - const: bus1
 67      - const: core
 68      - const: vcodec0_core
 69
 70required:
 71  - compatible
 72  - dma-coherent
 73  - interconnects
 74  - interconnect-names
 75  - iommus
 76  - power-domain-names
 77  - resets
 78  - reset-names
 79
 80allOf:
 81  - $ref: qcom,venus-common.yaml#
 82
 83unevaluatedProperties: false
 84
 85examples:
 86  - |
 87    #include <dt-bindings/clock/qcom,rpmh.h>
 88    #include <dt-bindings/clock/qcom,sm8750-gcc.h>
 89    #include <dt-bindings/interrupt-controller/arm-gic.h>
 90    #include <dt-bindings/interconnect/qcom,icc.h>
 91    #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h>
 92    #include <dt-bindings/power/qcom-rpmpd.h>
 93    #include <dt-bindings/power/qcom,rpmhpd.h>
 94
 95    video-codec@aa00000 {
 96        compatible = "qcom,sm8750-iris";
 97        reg = <0x0aa00000 0xf0000>;
 98
 99        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
100                 <&videocc_mvs0c_clk>,
101                 <&videocc_mvs0_clk>,
102                 <&gcc GCC_VIDEO_AXI1_CLK>,
103                 <&videocc_mvs0c_freerun_clk>,
104                 <&videocc_mvs0_freerun_clk>;
105        clock-names = "iface",
106                      "core",
107                      "vcodec0_core",
108                      "iface1",
109                      "core_freerun",
110                      "vcodec0_core_freerun";
111
112        dma-coherent;
113        iommus = <&apps_smmu 0x1940 0>,
114                 <&apps_smmu 0x1947 0>;
115
116        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
117                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
118                        <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
119                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
120        interconnect-names = "cpu-cfg",
121                             "video-mem";
122
123        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
124
125        operating-points-v2 = <&iris_opp_table>;
126
127        memory-region = <&video_mem>;
128
129        power-domains = <&videocc_mvs0c_gdsc>,
130                        <&videocc_mvs0_gdsc>,
131                        <&rpmhpd RPMHPD_MXC>,
132                        <&rpmhpd RPMHPD_MMCX>;
133        power-domain-names = "venus",
134                             "vcodec0",
135                             "mxc",
136                             "mmcx";
137
138        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
139                 <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
140                 <&videocc_mvs0c_freerun_clk_ares>,
141                 <&videocc_mvs0_freerun_clk_ares>;
142        reset-names = "bus0",
143                      "bus1",
144                      "core",
145                      "vcodec0_core";
146
147        iris_opp_table: opp-table {
148            compatible = "operating-points-v2";
149
150            opp-240000000 {
151                opp-hz = /bits/ 64 <240000000>;
152                required-opps = <&rpmhpd_opp_low_svs_d1>,
153                                <&rpmhpd_opp_low_svs_d1>;
154            };
155
156            opp-338000000 {
157                opp-hz = /bits/ 64 <338000000>;
158                required-opps = <&rpmhpd_opp_low_svs>,
159                                <&rpmhpd_opp_low_svs>;
160            };
161
162            opp-420000000 {
163                opp-hz = /bits/ 64 <420000000>;
164                required-opps = <&rpmhpd_opp_svs>,
165                                <&rpmhpd_opp_svs>;
166            };
167
168            opp-444000000 {
169                opp-hz = /bits/ 64 <444000000>;
170                required-opps = <&rpmhpd_opp_svs_l1>,
171                                <&rpmhpd_opp_svs_l1>;
172            };
173
174            opp-533333334 {
175                opp-hz = /bits/ 64 <533333334>;
176                required-opps = <&rpmhpd_opp_nom>,
177                                <&rpmhpd_opp_nom>;
178            };
179
180            opp-630000000 {
181                opp-hz = /bits/ 64 <630000000>;
182                required-opps = <&rpmhpd_opp_turbo>,
183                                <&rpmhpd_opp_turbo>;
184            };
185        };
186    };