qcom,sm8550-iris.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm iris video encode and decode accelerators
  8
  9maintainers:
 10  - Vikash Garodia <quic_vgarodia@quicinc.com>
 11  - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
 12
 13description:
 14  The iris video processing unit is a video encode and decode accelerator
 15  present on Qualcomm platforms.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - items:
 21          - enum:
 22              - qcom,sa8775p-iris
 23              - qcom,x1e80100-iris
 24          - const: qcom,sm8550-iris
 25      - enum:
 26          - qcom,qcs8300-iris
 27          - qcom,sm8550-iris
 28          - qcom,sm8650-iris
 29
 30  reg:
 31    maxItems: 1
 32
 33  power-domains:
 34    maxItems: 4
 35
 36  power-domain-names:
 37    items:
 38      - const: venus
 39      - const: vcodec0
 40      - const: mxc
 41      - const: mmcx
 42
 43  clocks:
 44    maxItems: 3
 45
 46  clock-names:
 47    items:
 48      - const: iface
 49      - const: core
 50      - const: vcodec0_core
 51
 52  firmware-name:
 53    maxItems: 1
 54
 55  interrupts:
 56    maxItems: 1
 57
 58  interconnects:
 59    maxItems: 2
 60
 61  interconnect-names:
 62    items:
 63      - const: cpu-cfg
 64      - const: video-mem
 65
 66  resets:
 67    minItems: 1
 68    maxItems: 3
 69
 70  reset-names:
 71    minItems: 1
 72    items:
 73      - const: bus
 74      - const: xo
 75      - const: core
 76
 77  iommus:
 78    maxItems: 2
 79
 80  dma-coherent: true
 81
 82  memory-region:
 83    maxItems: 1
 84
 85  operating-points-v2: true
 86
 87  opp-table:
 88    type: object
 89
 90required:
 91  - compatible
 92  - power-domain-names
 93  - interconnects
 94  - interconnect-names
 95  - resets
 96  - reset-names
 97  - iommus
 98  - dma-coherent
 99
100allOf:
101  - if:
102      properties:
103        compatible:
104          enum:
105            - qcom,sm8650-iris
106    then:
107      properties:
108        resets:
109          minItems: 3
110        reset-names:
111          minItems: 3
112    else:
113      properties:
114        resets:
115          maxItems: 1
116        reset-names:
117          maxItems: 1
118
119unevaluatedProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/clock/qcom,rpmh.h>
124    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
125    #include <dt-bindings/clock/qcom,sm8450-videocc.h>
126    #include <dt-bindings/interrupt-controller/arm-gic.h>
127    #include <dt-bindings/interconnect/qcom,icc.h>
128    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
129    #include <dt-bindings/power/qcom-rpmpd.h>
130    #include <dt-bindings/power/qcom,rpmhpd.h>
131
132    video-codec@aa00000 {
133        compatible = "qcom,sm8550-iris";
134        reg = <0x0aa00000 0xf0000>;
135        interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
136
137        power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
138                        <&videocc VIDEO_CC_MVS0_GDSC>,
139                        <&rpmhpd RPMHPD_MXC>,
140                        <&rpmhpd RPMHPD_MMCX>;
141        power-domain-names = "venus", "vcodec0", "mxc", "mmcx";
142
143        clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
144                 <&videocc VIDEO_CC_MVS0C_CLK>,
145                 <&videocc VIDEO_CC_MVS0_CLK>;
146        clock-names = "iface", "core", "vcodec0_core";
147
148        interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
149                         &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
150                        <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
151                         &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
152        interconnect-names = "cpu-cfg", "video-mem";
153
154        memory-region = <&video_mem>;
155
156        resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
157        reset-names = "bus";
158
159        iommus = <&apps_smmu 0x1940 0x0000>,
160                 <&apps_smmu 0x1947 0x0000>;
161        dma-coherent;
162
163        operating-points-v2 = <&iris_opp_table>;
164
165        iris_opp_table: opp-table {
166            compatible = "operating-points-v2";
167
168            opp-240000000 {
169                opp-hz = /bits/ 64 <240000000>;
170                required-opps = <&rpmhpd_opp_svs>,
171                                <&rpmhpd_opp_low_svs>;
172            };
173
174            opp-338000000 {
175                opp-hz = /bits/ 64 <338000000>;
176                required-opps = <&rpmhpd_opp_svs>,
177                                <&rpmhpd_opp_svs>;
178            };
179
180            opp-366000000 {
181                opp-hz = /bits/ 64 <366000000>;
182                required-opps = <&rpmhpd_opp_svs_l1>,
183                                <&rpmhpd_opp_svs_l1>;
184            };
185
186            opp-444000000 {
187                opp-hz = /bits/ 64 <444000000>;
188                required-opps = <&rpmhpd_opp_turbo>,
189                                <&rpmhpd_opp_turbo>;
190            };
191
192            opp-533333334 {
193                opp-hz = /bits/ 64 <533333334>;
194                required-opps = <&rpmhpd_opp_turbo_l1>,
195                                <&rpmhpd_opp_turbo_l1>;
196            };
197        };
198    };
199...