qcom,qcm2290-camss.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm QCM2290 Camera Subsystem (CAMSS)
  8
  9maintainers:
 10  - Loic Poulain <loic.poulain@oss.qualcomm.com>
 11
 12description:
 13  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
 14
 15properties:
 16  compatible:
 17    const: qcom,qcm2290-camss
 18
 19  reg:
 20    maxItems: 9
 21
 22  reg-names:
 23    items:
 24      - const: top
 25      - const: csid0
 26      - const: csid1
 27      - const: csiphy0
 28      - const: csiphy1
 29      - const: csitpg0
 30      - const: csitpg1
 31      - const: vfe0
 32      - const: vfe1
 33
 34  clocks:
 35    maxItems: 15
 36
 37  clock-names:
 38    items:
 39      - const: ahb
 40      - const: axi
 41      - const: camnoc_nrt_axi
 42      - const: camnoc_rt_axi
 43      - const: csi0
 44      - const: csi1
 45      - const: csiphy0
 46      - const: csiphy0_timer
 47      - const: csiphy1
 48      - const: csiphy1_timer
 49      - const: top_ahb
 50      - const: vfe0
 51      - const: vfe0_cphy_rx
 52      - const: vfe1
 53      - const: vfe1_cphy_rx
 54
 55  interrupts:
 56    maxItems: 8
 57
 58  interrupt-names:
 59    items:
 60      - const: csid0
 61      - const: csid1
 62      - const: csiphy0
 63      - const: csiphy1
 64      - const: csitpg0
 65      - const: csitpg1
 66      - const: vfe0
 67      - const: vfe1
 68
 69  interconnects:
 70    maxItems: 3
 71
 72  interconnect-names:
 73    items:
 74      - const: ahb
 75      - const: hf_mnoc
 76      - const: sf_mnoc
 77
 78  iommus:
 79    maxItems: 4
 80
 81  power-domains:
 82    items:
 83      - description: GDSC CAMSS Block, Global Distributed Switch Controller.
 84
 85  vdd-csiphy-1p2-supply:
 86    description:
 87      Phandle to a 1.2V regulator supply to CSI PHYs.
 88
 89  vdd-csiphy-1p8-supply:
 90    description:
 91      Phandle to 1.8V regulator supply to CSI PHYs pll block.
 92
 93  ports:
 94    $ref: /schemas/graph.yaml#/properties/ports
 95
 96    description:
 97      CSI input ports.
 98
 99    patternProperties:
100      "^port@[0-3]+$":
101        $ref: /schemas/graph.yaml#/$defs/port-base
102        unevaluatedProperties: false
103
104        description:
105          Input port for receiving CSI data from a CSIPHY.
106
107        properties:
108          endpoint:
109            $ref: video-interfaces.yaml#
110            unevaluatedProperties: false
111
112            properties:
113              data-lanes:
114                minItems: 1
115                maxItems: 4
116
117            required:
118              - data-lanes
119
120required:
121  - compatible
122  - reg
123  - reg-names
124  - clocks
125  - clock-names
126  - interrupts
127  - interrupt-names
128  - interconnects
129  - interconnect-names
130  - iommus
131  - power-domains
132  - vdd-csiphy-1p2-supply
133  - vdd-csiphy-1p8-supply
134
135additionalProperties: false
136
137examples:
138  - |
139    #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
140    #include <dt-bindings/interconnect/qcom,rpm-icc.h>
141    #include <dt-bindings/interconnect/qcom,qcm2290.h>
142    #include <dt-bindings/interrupt-controller/arm-gic.h>
143
144    soc {
145        #address-cells = <2>;
146        #size-cells = <2>;
147
148        camss: camss@5c6e000 {
149            compatible = "qcom,qcm2290-camss";
150
151            reg = <0x0 0x5c11000 0x0 0x1000>,
152                  <0x0 0x5c6e000 0x0 0x1000>,
153                  <0x0 0x5c75000 0x0 0x1000>,
154                  <0x0 0x5c52000 0x0 0x1000>,
155                  <0x0 0x5c53000 0x0 0x1000>,
156                  <0x0 0x5c66000 0x0 0x400>,
157                  <0x0 0x5c68000 0x0 0x400>,
158                  <0x0 0x5c6f000 0x0 0x4000>,
159                  <0x0 0x5c76000 0x0 0x4000>;
160            reg-names = "top",
161                        "csid0",
162                        "csid1",
163                        "csiphy0",
164                        "csiphy1",
165                        "csitpg0",
166                        "csitpg1",
167                        "vfe0",
168                        "vfe1";
169
170            clocks = <&gcc GCC_CAMERA_AHB_CLK>,
171                     <&gcc GCC_CAMSS_AXI_CLK>,
172                     <&gcc GCC_CAMSS_NRT_AXI_CLK>,
173                     <&gcc GCC_CAMSS_RT_AXI_CLK>,
174                     <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
175                     <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
176                     <&gcc GCC_CAMSS_CPHY_0_CLK>,
177                     <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
178                     <&gcc GCC_CAMSS_CPHY_1_CLK>,
179                     <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
180                     <&gcc GCC_CAMSS_TOP_AHB_CLK>,
181                     <&gcc GCC_CAMSS_TFE_0_CLK>,
182                     <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
183                     <&gcc GCC_CAMSS_TFE_1_CLK>,
184                     <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
185            clock-names = "ahb",
186                          "axi",
187                          "camnoc_nrt_axi",
188                          "camnoc_rt_axi",
189                          "csi0",
190                          "csi1",
191                          "csiphy0",
192                          "csiphy0_timer",
193                          "csiphy1",
194                          "csiphy1_timer",
195                          "top_ahb",
196                          "vfe0",
197                          "vfe0_cphy_rx",
198                          "vfe1",
199                          "vfe1_cphy_rx";
200
201            interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
202                         <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
203                         <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
204                         <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
205                         <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
206                         <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
207                         <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
208                         <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
209            interrupt-names = "csid0",
210                              "csid1",
211                              "csiphy0",
212                              "csiphy1",
213                              "csitpg0",
214                              "csitpg1",
215                              "vfe0",
216                              "vfe1";
217
218            interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
219                             &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>,
220                            <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG
221                             &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
222                            <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG
223                             &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
224            interconnect-names = "ahb",
225                                 "hf_mnoc",
226                                 "sf_mnoc";
227
228            iommus = <&apps_smmu 0x400 0x0>,
229                     <&apps_smmu 0x800 0x0>,
230                     <&apps_smmu 0x820 0x0>,
231                     <&apps_smmu 0x840 0x0>;
232
233            power-domains = <&gcc GCC_CAMSS_TOP_GDSC>;
234
235            vdd-csiphy-1p2-supply = <&pm4125_l5>;
236            vdd-csiphy-1p8-supply = <&pm4125_l13>;
237
238            ports {
239                #address-cells = <1>;
240                #size-cells = <0>;
241            };
242        };
243    };