nxp,imx8mq-mipi-csi2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NXP i.MX8MQ MIPI CSI-2 receiver
  8
  9maintainers:
 10  - Martin Kepplinger <martin.kepplinger@puri.sm>
 11
 12description: |-
 13  This binding covers the CSI-2 RX PHY and host controller included in the
 14  NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
 15  input imaging devices.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - enum:
 21          - fsl,imx8mq-mipi-csi2
 22          - fsl,imx8qxp-mipi-csi2
 23      - items:
 24          - const: fsl,imx8qm-mipi-csi2
 25          - const: fsl,imx8qxp-mipi-csi2
 26
 27  reg:
 28    items:
 29      - description: MIPI CSI-2 RX host controller register.
 30      - description: MIPI CSI-2 control and status register (csr).
 31    minItems: 1
 32
 33  clocks:
 34    items:
 35      - description: core is the RX Controller Core Clock input. This clock
 36                     must be exactly equal to or faster than the receive
 37                     byteclock from the RX DPHY.
 38      - description: esc is the Rx Escape Clock. This must be the same escape
 39                     clock that the RX DPHY receives.
 40      - description: ui is the pixel clock (phy_ref up to 333Mhz).
 41                     See the reference manual for details.
 42
 43  clock-names:
 44    items:
 45      - const: core
 46      - const: esc
 47      - const: ui
 48
 49  power-domains:
 50    maxItems: 1
 51
 52  resets:
 53    items:
 54      - description: CORE_RESET reset register bit definition
 55      - description: PHY_REF_RESET reset register bit definition
 56      - description: ESC_RESET reset register bit definition
 57    minItems: 1
 58
 59  fsl,mipi-phy-gpr:
 60    description: |
 61      The phandle to the imx8mq syscon iomux-gpr with the register
 62      for setting RX_ENABLE for the mipi receiver.
 63
 64      The format should be as follows:
 65      <gpr req_gpr>
 66      gpr is the phandle to general purpose register node.
 67      req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
 68    $ref: /schemas/types.yaml#/definitions/phandle-array
 69    items:
 70      - items:
 71          - description: The 'gpr' is the phandle to general purpose register node.
 72          - description: The 'req_gpr' is the gpr register offset containing
 73                        CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
 74            maximum: 0xff
 75
 76  interconnects:
 77    maxItems: 1
 78
 79  interconnect-names:
 80    const: dram
 81
 82  ports:
 83    $ref: /schemas/graph.yaml#/properties/ports
 84
 85    properties:
 86      port@0:
 87        $ref: /schemas/graph.yaml#/$defs/port-base
 88        unevaluatedProperties: false
 89        description:
 90          Input port node, single endpoint describing the CSI-2 transmitter.
 91
 92        properties:
 93          endpoint:
 94            $ref: video-interfaces.yaml#
 95            unevaluatedProperties: false
 96
 97            properties:
 98              data-lanes:
 99                minItems: 1
100                items:
101                  - const: 1
102                  - const: 2
103                  - const: 3
104                  - const: 4
105
106            required:
107              - data-lanes
108
109      port@1:
110        $ref: /schemas/graph.yaml#/properties/port
111        description:
112          Output port node
113
114    required:
115      - port@0
116      - port@1
117
118required:
119  - compatible
120  - reg
121  - clocks
122  - clock-names
123  - power-domains
124  - resets
125  - ports
126
127allOf:
128  - if:
129      properties:
130        compatible:
131          contains:
132            enum:
133              - fsl,imx8qxp-mipi-csi2
134    then:
135      properties:
136        reg:
137          minItems: 2
138        resets:
139          maxItems: 1
140    else:
141      properties:
142        reg:
143          maxItems: 1
144        resets:
145          minItems: 3
146      required:
147        - fsl,mipi-phy-gpr
148
149additionalProperties: false
150
151examples:
152  - |
153    #include <dt-bindings/clock/imx8mq-clock.h>
154    #include <dt-bindings/interconnect/imx8mq.h>
155    #include <dt-bindings/reset/imx8mq-reset.h>
156
157    csi@30a70000 {
158        compatible = "fsl,imx8mq-mipi-csi2";
159        reg = <0x30a70000 0x1000>;
160        clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
161                 <&clk IMX8MQ_CLK_CSI1_ESC>,
162                 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
163        clock-names = "core", "esc", "ui";
164        assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
165                          <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
166                          <&clk IMX8MQ_CLK_CSI1_ESC>;
167        assigned-clock-rates = <266000000>, <200000000>, <66000000>;
168        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
169                                 <&clk IMX8MQ_SYS2_PLL_1000M>,
170                                 <&clk IMX8MQ_SYS1_PLL_800M>;
171        power-domains = <&pgc_mipi_csi1>;
172        resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
173                 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
174                 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
175        fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
176        interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
177        interconnect-names = "dram";
178
179        ports {
180            #address-cells = <1>;
181            #size-cells = <0>;
182
183            port@0 {
184                reg = <0>;
185
186                imx8mm_mipi_csi_in: endpoint {
187                    remote-endpoint = <&imx477_out>;
188                    data-lanes = <1 2 3 4>;
189                };
190            };
191
192            port@1 {
193                reg = <1>;
194
195                imx8mm_mipi_csi_out: endpoint {
196                    remote-endpoint = <&csi_in>;
197                };
198            };
199        };
200    };
201
202...