nxp,imx-mipi-csi2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
  8
  9maintainers:
 10  - Rui Miguel Silva <rmfrfs@gmail.com>
 11  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
 12
 13description: |-
 14  The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
 15  receiver IP core named CSIS. The IP core originates from Samsung, and may be
 16  compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
 17  3.3, and i.MX8 SoCs use CSIS version 3.6.3.
 18
 19  While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
 20  completely wrapped by the CSIS and doesn't expose a control interface of its
 21  own. This binding thus covers both IP cores.
 22
 23properties:
 24  compatible:
 25    oneOf:
 26      - enum:
 27          - fsl,imx7-mipi-csi2
 28          - fsl,imx8mm-mipi-csi2
 29      - items:
 30          - enum:
 31              - fsl,imx8mp-mipi-csi2
 32          - const: fsl,imx8mm-mipi-csi2
 33
 34  reg:
 35    maxItems: 1
 36
 37  interrupts:
 38    maxItems: 1
 39
 40  clocks:
 41    minItems: 3
 42    items:
 43      - description: The peripheral clock (a.k.a. APB clock)
 44      - description: The external clock (optionally used as the pixel clock)
 45      - description: The MIPI D-PHY clock
 46      - description: The AXI clock
 47
 48  clock-names:
 49    minItems: 3
 50    items:
 51      - const: pclk
 52      - const: wrap
 53      - const: phy
 54      - const: axi
 55
 56  power-domains:
 57    maxItems: 1
 58
 59  phy-supply:
 60    description: The MIPI D-PHY digital power supply
 61
 62  resets:
 63    items:
 64      - description: MIPI D-PHY slave reset
 65
 66  clock-frequency:
 67    description: The desired external clock ("wrap") frequency, in Hz
 68    default: 166000000
 69    deprecated: true
 70
 71  fsl,num-channels:
 72    $ref: /schemas/types.yaml#/definitions/uint32
 73    description: Number of output channels
 74    minimum: 1
 75    maximum: 4
 76    default: 1
 77
 78  ports:
 79    $ref: /schemas/graph.yaml#/properties/ports
 80
 81    properties:
 82      port@0:
 83        $ref: /schemas/graph.yaml#/$defs/port-base
 84        unevaluatedProperties: false
 85        description:
 86          Input port node, single endpoint describing the CSI-2 transmitter.
 87
 88        properties:
 89          endpoint:
 90            $ref: video-interfaces.yaml#
 91            unevaluatedProperties: false
 92
 93            properties:
 94              data-lanes:
 95                description:
 96                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
 97                minItems: 1
 98                items:
 99                  - const: 1
100                  - const: 2
101                  - const: 3
102                  - const: 4
103
104            required:
105              - data-lanes
106
107      port@1:
108        $ref: /schemas/graph.yaml#/properties/port
109        description:
110          Output port node
111
112required:
113  - compatible
114  - reg
115  - interrupts
116  - clocks
117  - clock-names
118  - power-domains
119  - ports
120
121additionalProperties: false
122
123allOf:
124  - if:
125      properties:
126        compatible:
127          contains:
128            const: fsl,imx7-mipi-csi2
129    then:
130      required:
131        - phy-supply
132        - resets
133    else:
134      properties:
135        clocks:
136          minItems: 4
137        clock-names:
138          minItems: 4
139        phy-supply: false
140        resets: false
141
142examples:
143  - |
144    #include <dt-bindings/clock/imx7d-clock.h>
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146    #include <dt-bindings/interrupt-controller/irq.h>
147    #include <dt-bindings/reset/imx7-reset.h>
148
149    mipi-csi@30750000 {
150        compatible = "fsl,imx7-mipi-csi2";
151        reg = <0x30750000 0x10000>;
152        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
153
154        clocks = <&clks IMX7D_IPG_ROOT_CLK>,
155                 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
156                 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
157        clock-names = "pclk", "wrap", "phy";
158
159        assigned-clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>;
160        assigned-clock-rates = <166000000>;
161
162        power-domains = <&pgc_mipi_phy>;
163        phy-supply = <&reg_1p0d>;
164        resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
165
166        ports {
167            #address-cells = <1>;
168            #size-cells = <0>;
169
170            port@0 {
171                reg = <0>;
172
173                mipi_from_sensor: endpoint {
174                    remote-endpoint = <&ov2680_to_mipi>;
175                    data-lanes = <1>;
176                };
177            };
178
179            port@1 {
180                reg = <1>;
181
182                mipi_vc0_to_csi_mux: endpoint {
183                    remote-endpoint = <&csi_mux_from_mipi_vc0>;
184                };
185            };
186        };
187    };
188
189  - |
190    #include <dt-bindings/clock/imx8mm-clock.h>
191    #include <dt-bindings/interrupt-controller/arm-gic.h>
192    #include <dt-bindings/interrupt-controller/irq.h>
193
194    mipi-csi@32e30000 {
195        compatible = "fsl,imx8mm-mipi-csi2";
196        reg = <0x32e30000 0x1000>;
197        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
198
199        clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
200                 <&clk IMX8MM_CLK_CSI1_ROOT>,
201                 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
202                 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
203        clock-names = "pclk", "wrap", "phy", "axi";
204
205        assigned-clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
206        assigned-clock-rates = <250000000>;
207
208        power-domains = <&mipi_pd>;
209
210        ports {
211            #address-cells = <1>;
212            #size-cells = <0>;
213
214            port@0 {
215                reg = <0>;
216
217                imx8mm_mipi_csi_in: endpoint {
218                    remote-endpoint = <&imx477_out>;
219                    data-lanes = <1 2 3 4>;
220                };
221            };
222
223            port@1 {
224                reg = <1>;
225
226                imx8mm_mipi_csi_out: endpoint {
227                    remote-endpoint = <&csi_in>;
228                };
229            };
230        };
231    };
232
233...