microchip,csi2dc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/microchip,csi2dc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Microchip CSI2 Demux Controller (CSI2DC)
  8
  9maintainers:
 10  - Eugen Hristev <eugen.hristev@microchip.com>
 11
 12description:
 13  CSI2DC - Camera Serial Interface 2 Demux Controller
 14
 15  CSI2DC is a hardware block that receives incoming data from either from an
 16  IDI interface or from a parallel bus interface.
 17  It filters IDI packets based on their data type and virtual channel
 18  identifier, then converts the byte stream to a pixel stream into a cross
 19  clock domain towards a parallel interface that can be read by a sensor
 20  controller.
 21  IDI interface is Synopsys proprietary.
 22  CSI2DC can act a simple bypass bridge if the incoming data is coming from
 23  a parallel interface.
 24
 25  CSI2DC provides two pipes, one video pipe and one data pipe. Video pipe
 26  is connected at the output to a sensor controller and the data pipe is
 27  accessible as a DMA slave port to a DMA controller.
 28
 29  CSI2DC supports a single 'port' node as a sink port with either Synopsys
 30  32-bit IDI interface or a parallel interface.
 31
 32  CSI2DC supports one 'port' node as source port with parallel interface.
 33  This is called video pipe.
 34  This port has an 'endpoint' that can be connected to a sink port of another
 35  controller (next in pipeline).
 36
 37  CSI2DC also supports direct access to the data through AHB, via DMA channel,
 38  called data pipe.
 39  For data pipe to be available, a dma controller and a dma channel must be
 40  referenced.
 41
 42properties:
 43  compatible:
 44    const: microchip,sama7g5-csi2dc
 45
 46  reg:
 47    maxItems: 1
 48
 49  clocks:
 50    minItems: 2
 51    maxItems: 2
 52
 53  clock-names:
 54    description:
 55      CSI2DC must have two clocks to function correctly. One clock is the
 56      peripheral clock for the inside functionality of the hardware block.
 57      This is named 'pclk'. The second clock must be the cross domain clock,
 58      in which CSI2DC will perform clock crossing. This clock must be fed
 59      by the next controller in pipeline, which usually is a sensor controller.
 60      Normally this clock should be given by this sensor controller who
 61      is also a clock source. This clock is named 'scck', sensor controller clock.
 62    items:
 63      - const: pclk
 64      - const: scck
 65
 66  dmas:
 67    maxItems: 1
 68
 69  dma-names:
 70    const: rx
 71
 72  ports:
 73    $ref: /schemas/graph.yaml#/properties/ports
 74
 75    properties:
 76      port@0:
 77        $ref: /schemas/graph.yaml#/$defs/port-base
 78        unevaluatedProperties: false
 79        description:
 80          Input port node, single endpoint describing the input port.
 81
 82        properties:
 83          endpoint:
 84            $ref: video-interfaces.yaml#
 85            unevaluatedProperties: false
 86            description: Endpoint connected to input device
 87
 88            properties:
 89              bus-type:
 90                enum: [4, 5, 6]
 91                default: 4
 92
 93              bus-width:
 94                enum: [8, 9, 10, 11, 12, 13, 14]
 95                default: 14
 96
 97              clock-noncontinuous:
 98                type: boolean
 99                description:
100                  Presence of this boolean property decides whether clock is
101                  continuous or noncontinuous.
102
103              remote-endpoint: true
104
105      port@1:
106        $ref: /schemas/graph.yaml#/$defs/port-base
107        unevaluatedProperties: false
108        description:
109          Output port node, single endpoint describing the output port.
110
111        properties:
112          endpoint:
113            unevaluatedProperties: false
114            $ref: video-interfaces.yaml#
115            description: Endpoint connected to output device
116
117            properties:
118              bus-type:
119                enum: [5, 6]
120                default: 5
121
122              bus-width:
123                enum: [8, 9, 10, 11, 12, 13, 14]
124                default: 14
125
126              remote-endpoint: true
127
128    required:
129      - port@0
130      - port@1
131
132additionalProperties: false
133
134required:
135  - compatible
136  - reg
137  - clocks
138  - clock-names
139  - ports
140
141examples:
142  # Example for connecting to a parallel sensor controller block (video pipe)
143  # and the input is received from Synopsys IDI interface
144  - |
145    csi2dc@e1404000 {
146        compatible = "microchip,sama7g5-csi2dc";
147        reg = <0xe1404000 0x500>;
148        clocks = <&pclk>, <&scck>;
149        clock-names = "pclk", "scck";
150
151        ports {
152               #address-cells = <1>;
153               #size-cells = <0>;
154               port@0 {
155                       reg = <0>; /* must be 0, first child port */
156                       csi2dc_in: endpoint { /* input from IDI interface */
157                               bus-type = <4>; /* MIPI CSI2 D-PHY */
158                               remote-endpoint = <&csi2host_out>;
159                       };
160               };
161
162               port@1 {
163                       reg = <1>; /* must be 1, second child port */
164                       csi2dc_out: endpoint {
165                               remote-endpoint = <&xisc_in>; /* output to sensor controller */
166                       };
167               };
168        };
169    };
170
171  # Example for connecting to a DMA master as an AHB slave
172  # and the input is received from Synopsys IDI interface
173  - |
174    #include <dt-bindings/dma/at91.h>
175    csi2dc@e1404000 {
176        compatible = "microchip,sama7g5-csi2dc";
177        reg = <0xe1404000 0x500>;
178        clocks = <&pclk>, <&scck>;
179        clock-names = "pclk", "scck";
180        dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>;
181        dma-names = "rx";
182
183        ports {
184               #address-cells = <1>;
185               #size-cells = <0>;
186               port@0 {
187                       reg = <0>; /* must be 0, first child port */
188                       csi2dc_input: endpoint { /* input from IDI interface */
189                               remote-endpoint = <&csi2host_out>;
190                       };
191               };
192
193               port@1 {
194                       reg = <1>;
195               };
196        };
197    };
198
199...