mediatek,vcodec-encoder.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Mediatek Video Encode Accelerator
  8
  9maintainers:
 10  - Yunfei Dong <yunfei.dong@mediatek.com>
 11
 12description: |+
 13  Mediatek Video Encode is the video encode hardware present in Mediatek
 14  SoCs which supports high resolution encoding functionalities.
 15
 16properties:
 17  compatible:
 18    oneOf:
 19      - items:
 20          - enum:
 21              - mediatek,mt8173-vcodec-enc-vp8
 22              - mediatek,mt8173-vcodec-enc
 23              - mediatek,mt8183-vcodec-enc
 24              - mediatek,mt8188-vcodec-enc
 25              - mediatek,mt8192-vcodec-enc
 26              - mediatek,mt8195-vcodec-enc
 27      - items:
 28          - const: mediatek,mt8186-vcodec-enc
 29          - const: mediatek,mt8183-vcodec-enc
 30  reg:
 31    maxItems: 1
 32
 33  interrupts:
 34    maxItems: 1
 35
 36  clocks:
 37    minItems: 1
 38    maxItems: 5
 39
 40  clock-names:
 41    minItems: 1
 42    maxItems: 5
 43
 44  iommus:
 45    minItems: 1
 46    maxItems: 32
 47    description: |
 48      List of the hardware port in respective IOMMU block for current Socs.
 49      Refer to bindings/iommu/mediatek,iommu.yaml.
 50
 51  mediatek,vpu:
 52    $ref: /schemas/types.yaml#/definitions/phandle
 53    description:
 54      Describes point to vpu.
 55
 56  mediatek,scp:
 57    $ref: /schemas/types.yaml#/definitions/phandle
 58    description:
 59      Describes point to scp.
 60
 61  power-domains:
 62    maxItems: 1
 63
 64  "#address-cells":
 65    const: 2
 66
 67  "#size-cells":
 68    const: 2
 69
 70required:
 71  - compatible
 72  - reg
 73  - interrupts
 74  - clocks
 75  - clock-names
 76  - iommus
 77
 78allOf:
 79  - if:
 80      properties:
 81        compatible:
 82          contains:
 83            enum:
 84              - mediatek,mt8183-vcodec-enc
 85              - mediatek,mt8188-vcodec-enc
 86              - mediatek,mt8192-vcodec-enc
 87              - mediatek,mt8195-vcodec-enc
 88
 89    then:
 90      required:
 91        - mediatek,scp
 92
 93  - if:
 94      properties:
 95        compatible:
 96          contains:
 97            enum:
 98              - mediatek,mt8173-vcodec-enc-vp8
 99              - mediatek,mt8173-vcodec-enc
100
101    then:
102      required:
103        - mediatek,vpu
104
105  - if:
106      properties:
107        compatible:
108          enum:
109            - mediatek,mt8173-vcodec-enc-vp8
110
111    then:
112      properties:
113        clock:
114          items:
115            minItems: 1
116            maxItems: 1
117        clock-names:
118          items:
119            - const: venc_lt_sel
120    else:
121      properties:
122        clock:
123          items:
124            minItems: 1
125            maxItems: 1
126        clock-names:
127          items:
128            - const: venc_sel
129
130additionalProperties: false
131
132examples:
133  - |
134    #include <dt-bindings/interrupt-controller/arm-gic.h>
135    #include <dt-bindings/clock/mt8173-clk.h>
136    #include <dt-bindings/memory/mt8173-larb-port.h>
137    #include <dt-bindings/interrupt-controller/irq.h>
138
139    vcodec_enc_avc: vcodec@18002000 {
140      compatible = "mediatek,mt8173-vcodec-enc";
141      reg = <0x18002000 0x1000>;
142      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
143      iommus = <&iommu M4U_PORT_VENC_RCPU>,
144             <&iommu M4U_PORT_VENC_REC>,
145             <&iommu M4U_PORT_VENC_BSDMA>,
146             <&iommu M4U_PORT_VENC_SV_COMV>,
147             <&iommu M4U_PORT_VENC_RD_COMV>,
148             <&iommu M4U_PORT_VENC_CUR_LUMA>,
149             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
150             <&iommu M4U_PORT_VENC_REF_LUMA>,
151             <&iommu M4U_PORT_VENC_REF_CHROMA>,
152             <&iommu M4U_PORT_VENC_NBM_RDMA>,
153             <&iommu M4U_PORT_VENC_NBM_WDMA>;
154      mediatek,vpu = <&vpu>;
155      clocks = <&topckgen CLK_TOP_VENC_SEL>;
156      clock-names = "venc_sel";
157      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
158      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
159    };
160
161    vcodec_enc_vp8: vcodec@19002000 {
162      compatible = "mediatek,mt8173-vcodec-enc-vp8";
163      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
164      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
165      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
166             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
167             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
168             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
169             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
170             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
171             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
172             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
173             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
174      mediatek,vpu = <&vpu>;
175      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
176      clock-names = "venc_lt_sel";
177      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
178      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
179    };