mediatek,mt8173-mdp.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek MT8173 Media Data Path
  8
  9maintainers:
 10  - Ariel D'Alessandro <ariel.dalessandro@collabora.com>
 11
 12description:
 13  Media Data Path is used for scaling and color space conversion.
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - enum:
 19          - mediatek,mt8173-mdp-rdma
 20          - mediatek,mt8173-mdp-rsz
 21          - mediatek,mt8173-mdp-wdma
 22          - mediatek,mt8173-mdp-wrot
 23      - items:
 24          - const: mediatek,mt8173-mdp-rdma
 25          - const: mediatek,mt8173-mdp
 26
 27  reg:
 28    maxItems: 1
 29
 30  clocks:
 31    minItems: 1
 32    maxItems: 2
 33
 34  power-domains:
 35    maxItems: 1
 36
 37  iommus:
 38    maxItems: 1
 39
 40  mediatek,vpu:
 41    $ref: /schemas/types.yaml#/definitions/phandle
 42    description:
 43      phandle to Mediatek Video Processor Unit for HW Codec encode/decode and
 44      image processing.
 45
 46required:
 47  - compatible
 48  - reg
 49  - clocks
 50  - power-domains
 51
 52allOf:
 53  - if:
 54      properties:
 55        compatible:
 56          contains:
 57            const: mediatek,mt8173-mdp-rdma
 58    then:
 59      properties:
 60        clocks:
 61          items:
 62            - description: Main clock
 63            - description: Mutex clock
 64    else:
 65      properties:
 66        clocks:
 67          items:
 68            - description: Main clock
 69
 70  - if:
 71      properties:
 72        compatible:
 73          contains:
 74            enum:
 75              - mediatek,mt8173-mdp-rdma
 76              - mediatek,mt8173-mdp-wdma
 77              - mediatek,mt8173-mdp-wrot
 78    then:
 79      required:
 80        - iommus
 81
 82  - if:
 83      properties:
 84        compatible:
 85          contains:
 86            const: mediatek,mt8173-mdp
 87    then:
 88      required:
 89        - mediatek,vpu
 90
 91additionalProperties: false
 92
 93examples:
 94  - |
 95    #include <dt-bindings/clock/mt8173-clk.h>
 96    #include <dt-bindings/memory/mt8173-larb-port.h>
 97    #include <dt-bindings/power/mt8173-power.h>
 98
 99    soc {
100        #address-cells = <2>;
101        #size-cells = <2>;
102
103        mdp_rdma0: rdma@14001000 {
104            compatible = "mediatek,mt8173-mdp-rdma",
105                         "mediatek,mt8173-mdp";
106            reg = <0 0x14001000 0 0x1000>;
107            clocks = <&mmsys CLK_MM_MDP_RDMA0>,
108                     <&mmsys CLK_MM_MUTEX_32K>;
109            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
110            iommus = <&iommu M4U_PORT_MDP_RDMA0>;
111            mediatek,vpu = <&vpu>;
112        };
113
114        mdp_rdma1: rdma@14002000 {
115            compatible = "mediatek,mt8173-mdp-rdma";
116            reg = <0 0x14002000 0 0x1000>;
117            clocks = <&mmsys CLK_MM_MDP_RDMA1>,
118                     <&mmsys CLK_MM_MUTEX_32K>;
119            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
120            iommus = <&iommu M4U_PORT_MDP_RDMA1>;
121        };
122
123        mdp_rsz0: rsz@14003000 {
124            compatible = "mediatek,mt8173-mdp-rsz";
125            reg = <0 0x14003000 0 0x1000>;
126            clocks = <&mmsys CLK_MM_MDP_RSZ0>;
127            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
128        };
129
130        mdp_rsz1: rsz@14004000 {
131            compatible = "mediatek,mt8173-mdp-rsz";
132            reg = <0 0x14004000 0 0x1000>;
133            clocks = <&mmsys CLK_MM_MDP_RSZ1>;
134            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
135        };
136
137        mdp_rsz2: rsz@14005000 {
138            compatible = "mediatek,mt8173-mdp-rsz";
139            reg = <0 0x14005000 0 0x1000>;
140            clocks = <&mmsys CLK_MM_MDP_RSZ2>;
141            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
142        };
143
144        mdp_wdma0: wdma@14006000 {
145            compatible = "mediatek,mt8173-mdp-wdma";
146            reg = <0 0x14006000 0 0x1000>;
147            clocks = <&mmsys CLK_MM_MDP_WDMA>;
148            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
149            iommus = <&iommu M4U_PORT_MDP_WDMA>;
150        };
151
152        mdp_wrot0: wrot@14007000 {
153            compatible = "mediatek,mt8173-mdp-wrot";
154            reg = <0 0x14007000 0 0x1000>;
155            clocks = <&mmsys CLK_MM_MDP_WROT0>;
156            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
157            iommus = <&iommu M4U_PORT_MDP_WROT0>;
158        };
159
160        mdp_wrot1: wrot@14008000 {
161            compatible = "mediatek,mt8173-mdp-wrot";
162            reg = <0 0x14008000 0 0x1000>;
163            clocks = <&mmsys CLK_MM_MDP_WROT1>;
164            power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
165            iommus = <&iommu M4U_PORT_MDP_WROT1>;
166        };
167    };
168
169...