mediatek,mdp3-hdr.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: MediaTek Media Data Path 3 HDR
 8
 9maintainers:
10  - Matthias Brugger <matthias.bgg@gmail.com>
11  - Moudy Ho <moudy.ho@mediatek.com>
12
13description:
14  A Media Data Path 3 (MDP3) component used to perform conversion from
15  High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
16
17properties:
18  compatible:
19    oneOf:
20      - enum:
21          - mediatek,mt8195-mdp3-hdr
22      - items:
23          - const: mediatek,mt8188-mdp3-hdr
24          - const: mediatek,mt8195-mdp3-hdr
25
26  reg:
27    maxItems: 1
28
29  mediatek,gce-client-reg:
30    description:
31      The register of display function block to be set by gce. There are 4 arguments,
32      such as gce node, subsys id, offset and register size. The subsys id that is
33      mapping to the register of display function blocks is defined in the gce header
34      include/dt-bindings/gce/<chip>-gce.h of each chips.
35    $ref: /schemas/types.yaml#/definitions/phandle-array
36    items:
37      items:
38        - description: phandle of GCE
39        - description: GCE subsys id
40        - description: register offset
41        - description: register size
42    maxItems: 1
43
44  clocks:
45    maxItems: 1
46
47required:
48  - compatible
49  - reg
50  - mediatek,gce-client-reg
51  - clocks
52
53additionalProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/mt8195-clk.h>
58    #include <dt-bindings/gce/mt8195-gce.h>
59
60    display@14004000 {
61        compatible = "mediatek,mt8195-mdp3-hdr";
62        reg = <0x14004000 0x1000>;
63        mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
64        clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
65    };