nxp,tda19971.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/i2c/nxp,tda19971.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NXP TDA1997x HDMI receiver
  8
  9maintainers:
 10  - Frank Li <Frank.Li@nxp.com>
 11
 12description: |
 13  The TDA19971/73 are HDMI video receivers.
 14
 15  The TDA19971 Video port output pins can be used as follows:
 16   - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
 17   - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
 18   - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
 19   - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
 20   - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
 21   - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
 22   - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
 23   - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
 24
 25  The TDA19973 Video port output pins can be used as follows:
 26   - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
 27   - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
 28   - YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
 29   - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
 30
 31  The Video port output pins are mapped via 4-bit 'pin groups' allowing
 32  for a variety of connection possibilities including swapping pin order within
 33  pin groups. The video_portcfg device-tree property consists of register mapping
 34  pairs which map a chip-specific VP output register to a 4-bit pin group. If
 35  the pin group needs to be bit-swapped you can use the *_S pin-group defines.
 36
 37properties:
 38  compatible:
 39    enum:
 40      - nxp,tda19971
 41      - nxp,tda19973
 42
 43  reg:
 44    maxItems: 1
 45
 46  interrupts:
 47    maxItems: 1
 48
 49  DOVDD-supply: true
 50
 51  DVDD-supply: true
 52
 53  AVDD-supply: true
 54
 55  '#sound-dai-cells':
 56    const: 0
 57
 58  port:
 59    $ref: /schemas/graph.yaml#/$defs/port-base
 60    unevaluatedProperties: false
 61
 62    properties:
 63      endpoint:
 64        $ref: /schemas/media/video-interfaces.yaml#
 65        unevaluatedProperties: false
 66
 67  nxp,vidout-portcfg:
 68    $ref: /schemas/types.yaml#/definitions/uint32-matrix
 69    minItems: 1
 70    maxItems: 4
 71    items:
 72      items:
 73        - description: Video Port control registers index.
 74          maximum: 8
 75          minimum: 0
 76        - description: pin(pinswapped) groups
 77
 78    description:
 79      array of pairs mapping VP output pins to pin groups.
 80
 81  nxp,audout-format:
 82    enum:
 83      - i2s
 84      - spdif
 85
 86  nxp,audout-width:
 87    $ref: /schemas/types.yaml#/definitions/uint32
 88    enum: [8, 16, 24, 32]
 89    description:
 90      width of audio output data bus.
 91
 92  nxp,audout-layout:
 93    $ref: /schemas/types.yaml#/definitions/uint32
 94    enum: [0, 1]
 95    description:
 96      data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
 97
 98  nxp,audout-mclk-fs:
 99    $ref: /schemas/types.yaml#/definitions/uint32
100    description:
101      Multiplication factor between stream rate and codec mclk.
102
103required:
104  - compatible
105  - reg
106  - interrupts
107  - DOVDD-supply
108  - AVDD-supply
109  - DVDD-supply
110
111additionalProperties: false
112
113examples:
114  - |
115    #include <dt-bindings/interrupt-controller/irq.h>
116    #include <dt-bindings/media/tda1997x.h>
117
118    i2c {
119        #address-cells = <1>;
120        #size-cells = <0>;
121
122        hdmi-receiver@48 {
123            compatible = "nxp,tda19971";
124            reg = <0x48>;
125            pinctrl-names = "default";
126            pinctrl-0 = <&pinctrl_tda1997x>;
127            interrupt-parent = <&gpio1>;
128            interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
129            DOVDD-supply = <&reg_3p3v>;
130            AVDD-supply = <&reg_1p8v>;
131            DVDD-supply = <&reg_1p8v>;
132            /* audio */
133            #sound-dai-cells = <0>;
134            nxp,audout-format = "i2s";
135            nxp,audout-layout = <0>;
136            nxp,audout-width = <16>;
137            nxp,audout-mclk-fs = <128>;
138            /*
139             * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
140             * and Y[11:4] across 16bits in the same pixclk cycle.
141             */
142            nxp,vidout-portcfg =
143                /* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
144                < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
145                /* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
146                < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
147                /* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
148                < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
149                /* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
150                < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
151
152            port {
153                endpoint {
154                    remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
155                    bus-width = <16>;
156                    hsync-active = <1>;
157                    vsync-active = <1>;
158                    data-active = <1>;
159                };
160            };
161        };
162    };