fsl,imx8qxp-isi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/fsl,imx8qxp-isi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: i.MX8QXP Image Sensing Interface
  8
  9maintainers:
 10  - Frank Li <Frank.Li@nxp.com>
 11
 12description:
 13  The Image Sensing Interface (ISI) combines image processing pipelines with
 14  DMA engines to process and capture frames originating from a variety of
 15  sources. The inputs to the ISI go through Pixel Link interfaces, and their
 16  number and nature is SoC-dependent. They cover both capture interfaces (MIPI
 17  CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
 18
 19properties:
 20  compatible:
 21    enum:
 22      - fsl,imx8qxp-isi
 23
 24  reg:
 25    maxItems: 1
 26
 27  clocks:
 28    maxItems: 6
 29
 30  clock-names:
 31    items:
 32      - const: per0
 33      - const: per1
 34      - const: per2
 35      - const: per3
 36      - const: per4
 37      - const: per5
 38
 39  interrupts:
 40    maxItems: 6
 41
 42  power-domains:
 43    maxItems: 6
 44
 45  ports:
 46    $ref: /schemas/graph.yaml#/properties/ports
 47    properties:
 48      port@2:
 49        $ref: /schemas/graph.yaml#/properties/port
 50        description: MIPI CSI-2 RX 0
 51      port@6:
 52        $ref: /schemas/graph.yaml#/properties/port
 53        description: CSI-2 Parallel RX
 54
 55required:
 56  - compatible
 57  - reg
 58  - clocks
 59  - clock-names
 60  - interrupts
 61  - power-domains
 62  - ports
 63
 64additionalProperties: false
 65
 66examples:
 67  - |
 68    #include <dt-bindings/interrupt-controller/arm-gic.h>
 69    #include <dt-bindings/interrupt-controller/irq.h>
 70    #include <dt-bindings/clock/imx8-clock.h>
 71    #include <dt-bindings/clock/imx8-lpcg.h>
 72    #include <dt-bindings/firmware/imx/rsrc.h>
 73
 74    image-controller@58100000 {
 75        compatible = "fsl,imx8qxp-isi";
 76        reg = <0x58100000 0x60000>;
 77        interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 78                     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
 79                     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
 80                     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
 81                     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
 82                     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
 83        clocks = <&pdma0_lpcg IMX_LPCG_CLK_0>,
 84                 <&pdma1_lpcg IMX_LPCG_CLK_0>,
 85                 <&pdma2_lpcg IMX_LPCG_CLK_0>,
 86                 <&pdma3_lpcg IMX_LPCG_CLK_0>,
 87                 <&pdma4_lpcg IMX_LPCG_CLK_0>,
 88                 <&pdma5_lpcg IMX_LPCG_CLK_0>;
 89        clock-names = "per0", "per1", "per2", "per3", "per4", "per5";
 90        power-domains = <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH1>,
 91                        <&pd IMX_SC_R_ISI_CH2>, <&pd IMX_SC_R_ISI_CH3>,
 92                        <&pd IMX_SC_R_ISI_CH4>, <&pd IMX_SC_R_ISI_CH5>;
 93
 94        ports {
 95            #address-cells = <1>;
 96            #size-cells = <0>;
 97
 98            port@2 {
 99                reg = <2>;
100                endpoint {
101                    remote-endpoint = <&mipi_csi0_out>;
102                };
103            };
104        };
105    };
106...