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fsl,imx6ull-pxp.yaml
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linux-6.19.14/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Freescale Pixel Pipeline 8 9maintainers: 10 - Philipp Zabel <p.zabel@pengutronix.de> 11 - Michael Tretter <m.tretter@pengutronix.de> 12 13description: 14 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine 15 that supports scaling, colorspace conversion, alpha blending, rotation, and 16 pixel conversion via lookup table. Different versions are present on various 17 i.MX SoCs from i.MX23 to i.MX7. 18 19properties: 20 compatible: 21 oneOf: 22 - enum: 23 - fsl,imx6ul-pxp 24 - fsl,imx6ull-pxp 25 - fsl,imx7d-pxp 26 - items: 27 - enum: 28 - fsl,imx6sll-pxp 29 - fsl,imx6sx-pxp 30 - const: fsl,imx6ull-pxp 31 32 reg: 33 maxItems: 1 34 35 interrupts: 36 minItems: 1 37 maxItems: 2 38 39 clocks: 40 maxItems: 1 41 42 clock-names: 43 const: axi 44 45 power-domains: 46 maxItems: 1 47 48required: 49 - compatible 50 - reg 51 - interrupts 52 - clocks 53 - clock-names 54 55allOf: 56 - if: 57 properties: 58 compatible: 59 contains: 60 enum: 61 - fsl,imx6sx-pxp 62 - fsl,imx6ul-pxp 63 then: 64 properties: 65 interrupts: 66 maxItems: 1 67 else: 68 properties: 69 interrupts: 70 minItems: 2 71 maxItems: 2 72 73additionalProperties: false 74 75examples: 76 - | 77 #include <dt-bindings/clock/imx6ul-clock.h> 78 #include <dt-bindings/interrupt-controller/arm-gic.h> 79 80 pxp: pxp@21cc000 { 81 compatible = "fsl,imx6ull-pxp"; 82 reg = <0x021cc000 0x4000>; 83 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 85 clock-names = "axi"; 86 clocks = <&clks IMX6UL_CLK_PXP>; 87 };
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