fsl,imx6-mipi-csi2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/fsl,imx6-mipi-csi2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MIPI CSI-2 Receiver core in the i.MX SoC
  8
  9description:
 10  This is the device node for the MIPI CSI-2 Receiver core in the i.MX
 11  SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
 12  combined with a D-PHY core mixed into the same register block. In
 13  addition this device consists of an i.MX-specific "CSI2IPU gasket"
 14  glue logic, also controlled from the same register block. The CSI2IPU
 15  gasket demultiplexes the four virtual channel streams from the host
 16  controller's 32-bit output image bus onto four 16-bit parallel busses
 17  to the i.MX IPU CSIs.
 18
 19maintainers:
 20  - Frank Li <Frank.Li@nxp.com>
 21
 22properties:
 23  compatible:
 24    const: fsl,imx6-mipi-csi2
 25
 26  reg:
 27    maxItems: 1
 28
 29  clocks:
 30    items:
 31      - description: hsi_tx (the D-PHY clock)
 32      - description: video_27m (D-PHY PLL reference clock)
 33      - description: eim_podf;
 34
 35  clock-names:
 36    items:
 37      - const: dphy
 38      - const: ref
 39      - const: pix
 40
 41  interrupts:
 42    items:
 43      - description: CSI-2 ERR1 irq
 44      - description: CSI-2 ERR2 irq
 45
 46  '#address-cells':
 47    const: 1
 48
 49  '#size-cells':
 50    const: 0
 51
 52  port@0:
 53    $ref: /schemas/graph.yaml#/$defs/port-base
 54    unevaluatedProperties: false
 55    description:
 56      Input port node, single endpoint describing the CSI-2 transmitter.
 57
 58    properties:
 59      endpoint:
 60        $ref: video-interfaces.yaml#
 61        unevaluatedProperties: false
 62
 63        properties:
 64          clock-lanes:
 65            const: 0
 66
 67          data-lanes:
 68            minItems: 1
 69            items:
 70              - const: 1
 71              - const: 2
 72              - const: 3
 73              - const: 4
 74
 75        required:
 76          - data-lanes
 77
 78patternProperties:
 79  '^port@[1-4]$':
 80    $ref: /schemas/graph.yaml#/$defs/port-base
 81    unevaluatedProperties: false
 82    description:
 83      ports 1 through 4 are output ports connecting with parallel bus sink
 84      endpoint nodes and correspond to the four MIPI CSI-2 virtual channel
 85      outputs.
 86
 87    properties:
 88      endpoint@0:
 89        $ref: video-interfaces.yaml#
 90        unevaluatedProperties: false
 91
 92      endpoint@1:
 93        $ref: video-interfaces.yaml#
 94        unevaluatedProperties: false
 95
 96required:
 97  - compatible
 98  - reg
 99  - clocks
100  - clock-names
101
102additionalProperties: false
103
104examples:
105  - |
106    #include <dt-bindings/clock/imx6qdl-clock.h>
107
108    mipi@21dc000 {
109        compatible = "fsl,imx6-mipi-csi2";
110        reg = <0x021dc000 0x4000>;
111        #address-cells = <1>;
112        #size-cells = <0>;
113        clocks = <&clks IMX6QDL_CLK_HSI_TX>,
114                 <&clks IMX6QDL_CLK_VIDEO_27M>,
115                 <&clks IMX6QDL_CLK_EIM_PODF>;
116        clock-names = "dphy", "ref", "pix";
117
118        port@0 {
119            reg = <0>;
120
121            endpoint {
122                remote-endpoint = <&ov5640_to_mipi_csi2>;
123                clock-lanes = <0>;
124                data-lanes = <1 2>;
125            };
126        };
127
128        port@1 {
129            reg = <1>;
130            #address-cells = <1>;
131            #size-cells = <0>;
132
133            endpoint@0 {
134                reg = <0>;
135                remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
136            };
137
138            endpoint@1 {
139                reg = <1>;
140                remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
141            };
142        };
143    };