amphion,vpu.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Amphion VPU codec IP
  8
  9maintainers:
 10  - Ming Qian <ming.qian@nxp.com>
 11  - Shijie Qin <shijie.qin@nxp.com>
 12
 13description: |-
 14  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
 15  on NXP i.MX8Q SoCs.
 16
 17properties:
 18  $nodename:
 19    pattern: "^vpu@[0-9a-f]+$"
 20
 21  compatible:
 22    items:
 23      - enum:
 24          - nxp,imx8qm-vpu
 25          - nxp,imx8qxp-vpu
 26
 27  reg:
 28    maxItems: 1
 29
 30  power-domains:
 31    maxItems: 1
 32
 33  "#address-cells":
 34    const: 1
 35
 36  "#size-cells":
 37    const: 1
 38
 39  ranges: true
 40
 41patternProperties:
 42  "^mailbox@[0-9a-f]+$":
 43    description:
 44      Each vpu encoder or decoder correspond a MU, which used for communication
 45      between driver and firmware. Implement via mailbox on driver.
 46    $ref: /schemas/mailbox/fsl,mu.yaml#
 47
 48  "^vpu-core@[0-9a-f]+$":
 49    description:
 50      Each core correspond a decoder or encoder, need to configure them
 51      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
 52      has one decoder and one encoder.
 53    type: object
 54
 55    properties:
 56      compatible:
 57        items:
 58          - enum:
 59              - nxp,imx8q-vpu-decoder
 60              - nxp,imx8q-vpu-encoder
 61
 62      reg:
 63        maxItems: 1
 64
 65      power-domains:
 66        maxItems: 1
 67
 68      mbox-names:
 69        items:
 70          - const: tx0
 71          - const: tx1
 72          - const: rx
 73
 74      mboxes:
 75        description:
 76          List of phandle of 2 MU channels for tx, 1 MU channel for rx.
 77        maxItems: 3
 78
 79      memory-region:
 80        description:
 81          Phandle to the reserved memory nodes to be associated with the
 82          remoteproc device. The reserved memory nodes should be carveout nodes,
 83          and should be defined as per the bindings in
 84          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
 85        items:
 86          - description: region reserved for firmware image sections.
 87          - description: region used for RPC shared memory between firmware and
 88                         driver.
 89
 90    required:
 91      - compatible
 92      - reg
 93      - power-domains
 94      - mbox-names
 95      - mboxes
 96      - memory-region
 97
 98    additionalProperties: false
 99
100required:
101  - compatible
102  - reg
103  - power-domains
104
105additionalProperties: false
106
107examples:
108  # Device node example for i.MX8QM platform:
109  - |
110    #include <dt-bindings/firmware/imx/rsrc.h>
111
112    vpu: vpu@2c000000 {
113      compatible = "nxp,imx8qm-vpu";
114      ranges = <0x2c000000 0x2c000000 0x2000000>;
115      reg = <0x2c000000 0x1000000>;
116      #address-cells = <1>;
117      #size-cells = <1>;
118      power-domains = <&pd IMX_SC_R_VPU>;
119
120      mu_m0: mailbox@2d000000 {
121        compatible = "fsl,imx6sx-mu";
122        reg = <0x2d000000 0x20000>;
123        interrupts = <0 472 4>;
124        #mbox-cells = <2>;
125        power-domains = <&pd IMX_SC_R_VPU_MU_0>;
126      };
127
128      mu1_m0: mailbox@2d020000 {
129        compatible = "fsl,imx6sx-mu";
130        reg = <0x2d020000 0x20000>;
131        interrupts = <0 473 4>;
132        #mbox-cells = <2>;
133        power-domains = <&pd IMX_SC_R_VPU_MU_1>;
134      };
135
136      mu2_m0: mailbox@2d040000 {
137        compatible = "fsl,imx6sx-mu";
138        reg = <0x2d040000 0x20000>;
139        interrupts = <0 474 4>;
140        #mbox-cells = <2>;
141        power-domains = <&pd IMX_SC_R_VPU_MU_2>;
142      };
143
144      vpu_core0: vpu-core@2d080000 {
145        compatible = "nxp,imx8q-vpu-decoder";
146        reg = <0x2d080000 0x10000>;
147        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
148        mbox-names = "tx0", "tx1", "rx";
149        mboxes = <&mu_m0 0 0>,
150                 <&mu_m0 0 1>,
151                 <&mu_m0 1 0>;
152        memory-region = <&decoder_boot>, <&decoder_rpc>;
153      };
154
155      vpu_core1: vpu-core@2d090000 {
156        compatible = "nxp,imx8q-vpu-encoder";
157        reg = <0x2d090000 0x10000>;
158        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
159        mbox-names = "tx0", "tx1", "rx";
160        mboxes = <&mu1_m0 0 0>,
161                 <&mu1_m0 0 1>,
162                 <&mu1_m0 1 0>;
163        memory-region = <&encoder1_boot>, <&encoder1_rpc>;
164      };
165
166      vpu_core2: vpu-core@2d0a0000 {
167        reg = <0x2d0a0000 0x10000>;
168        compatible = "nxp,imx8q-vpu-encoder";
169        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
170        mbox-names = "tx0", "tx1", "rx";
171        mboxes = <&mu2_m0 0 0>,
172                 <&mu2_m0 0 1>,
173                 <&mu2_m0 1 0>;
174        memory-region = <&encoder2_boot>, <&encoder2_rpc>;
175      };
176    };
177
178...