microchip,sbi-ipc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Microchip Inter-processor communication (IPC) mailbox controller
  8
  9maintainers:
 10  - Valentina Fernandez <valentina.fernandezalanis@microchip.com>
 11
 12description:
 13  The Microchip Inter-processor Communication (IPC) facilitates
 14  message passing between processors using an interrupt signaling
 15  mechanism.
 16
 17properties:
 18  compatible:
 19    oneOf:
 20      - description:
 21          Intended for use by software running in supervisor privileged
 22          mode (s-mode). This SBI interface is compatible with the Mi-V
 23          Inter-hart Communication (IHC) IP.
 24        const: microchip,sbi-ipc
 25
 26      - description:
 27          Intended for use by the SBI implementation in machine mode
 28          (m-mode), this compatible string is for the MIV_IHC Soft-IP.
 29        const: microchip,miv-ihc-rtl-v2
 30
 31  reg:
 32    maxItems: 1
 33
 34  interrupts:
 35    minItems: 1
 36    maxItems: 5
 37
 38  interrupt-names:
 39    minItems: 1
 40    maxItems: 5
 41    items:
 42      enum:
 43        - hart-0
 44        - hart-1
 45        - hart-2
 46        - hart-3
 47        - hart-4
 48        - hart-5
 49
 50  "#mbox-cells":
 51    description: >
 52      For "microchip,sbi-ipc", the cell represents the global "logical"
 53      channel IDs. The meaning of channel IDs are platform firmware dependent.
 54
 55      For "microchip,miv-ihc-rtl-v2", the cell represents the physical
 56      channel and does not vary based on the platform firmware.
 57    const: 1
 58
 59  microchip,ihc-chan-disabled-mask:
 60    description: >
 61      Represents the enable/disable state of the bi-directional IHC
 62      channels within the MIV-IHC IP configuration.
 63
 64      A bit set to '1' indicates that the corresponding channel is disabled,
 65      and any read or write operations to that channel will return zero.
 66
 67      A bit set to '0' indicates that the corresponding channel is enabled
 68      and will be accessible through its dedicated address range registers.
 69
 70      The actual enable/disable state of each channel is determined by the
 71      IP block’s configuration.
 72    $ref: /schemas/types.yaml#/definitions/uint16
 73    maximum: 0x7fff
 74    default: 0
 75
 76required:
 77  - compatible
 78  - interrupts
 79  - interrupt-names
 80  - "#mbox-cells"
 81
 82allOf:
 83  - if:
 84      properties:
 85        compatible:
 86          contains:
 87            const: microchip,sbi-ipc
 88    then:
 89      properties:
 90        reg:
 91          not: {}
 92          description:
 93            The 'microchip,sbi-ipc' operates in a programming model
 94            that does not require memory-mapped I/O (MMIO) registers
 95            since it uses SBI ecalls provided by the m-mode/firmware
 96            SBI implementation to access hardware registers.
 97        microchip,ihc-chan-disabled-mask: false
 98    else:
 99      required:
100        - reg
101        - microchip,ihc-chan-disabled-mask
102
103additionalProperties: false
104
105examples:
106  - |
107    mailbox {
108      compatible = "microchip,sbi-ipc";
109      interrupt-parent = <&plic>;
110      interrupts = <180>, <179>, <178>;
111      interrupt-names = "hart-1", "hart-2", "hart-3";
112      #mbox-cells = <1>;
113    };
114  - |
115    mailbox@50000000 {
116      compatible = "microchip,miv-ihc-rtl-v2";
117      microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
118      reg = <0x50000000 0x1c000>;
119      interrupt-parent = <&plic>;
120      interrupts = <180>, <179>, <178>;
121      interrupt-names = "hart-1", "hart-2", "hart-3";
122      #mbox-cells = <1>;
123    };