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aspeed,ast2400-kcs-bmc.yaml

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linux-6.19.14/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml YAML
  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ASPEED BMC KCS Devices
  8
  9maintainers:
 10  - Andrew Jeffery <andrew@aj.id.au>
 11
 12description: |
 13  The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
 14  interfaces on the LPC bus for in-band IPMI communication with their host.
 15
 16properties:
 17  compatible:
 18    oneOf:
 19      - description: Channel ID derived from reg
 20        items:
 21          enum:
 22            - aspeed,ast2400-kcs-bmc-v2
 23            - aspeed,ast2500-kcs-bmc-v2
 24            - aspeed,ast2600-kcs-bmc
 25
 26      - description: Old-style with explicit channel ID, no reg
 27        deprecated: true
 28        items:
 29          enum:
 30            - aspeed,ast2400-kcs-bmc
 31            - aspeed,ast2500-kcs-bmc
 32
 33  interrupts:
 34    maxItems: 1
 35
 36  reg:
 37    # maxItems: 3
 38    items:
 39      - description: IDR register
 40      - description: ODR register
 41      - description: STR register
 42
 43  clocks:
 44    maxItems: 1
 45
 46  aspeed,lpc-io-reg:
 47    $ref: /schemas/types.yaml#/definitions/uint32-array
 48    minItems: 1
 49    maxItems: 2
 50    description: |
 51      The host CPU LPC IO data and status addresses for the device. For most
 52      channels the status address is derived from the data address, but the
 53      status address may be optionally provided.
 54
 55  aspeed,lpc-interrupts:
 56    $ref: /schemas/types.yaml#/definitions/uint32-array
 57    minItems: 2
 58    maxItems: 2
 59    description: |
 60      A 2-cell property expressing the LPC SerIRQ number and the interrupt
 61      level/sense encoding (specified in the standard fashion).
 62
 63      Note that the generated interrupt is issued from the BMC to the host, and
 64      thus the target interrupt controller is not captured by the BMC's
 65      devicetree.
 66
 67  kcs_chan:
 68    deprecated: true
 69    $ref: /schemas/types.yaml#/definitions/uint32
 70    description: The LPC channel number in the controller
 71
 72  kcs_addr:
 73    deprecated: true
 74    $ref: /schemas/types.yaml#/definitions/uint32
 75    description: The host CPU IO map address
 76
 77required:
 78  - compatible
 79  - interrupts
 80
 81additionalProperties: false
 82
 83allOf:
 84  - if:
 85      properties:
 86        compatible:
 87          contains:
 88            enum:
 89              - aspeed,ast2400-kcs-bmc
 90              - aspeed,ast2500-kcs-bmc
 91    then:
 92      required:
 93        - kcs_chan
 94        - kcs_addr
 95    else:
 96      required:
 97        - reg
 98        - aspeed,lpc-io-reg
 99
100examples:
101  - |
102    #include <dt-bindings/interrupt-controller/irq.h>
103    kcs3: kcs@24 {
104        compatible = "aspeed,ast2600-kcs-bmc";
105        reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
106        aspeed,lpc-io-reg = <0xca2>;
107        aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
108        interrupts = <8>;
109    };
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