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arm,smmu.yaml
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linux-6.19.14/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - qcom,sm6375-smmu-v2 33 - const: qcom,smmu-v2 34 35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 36 items: 37 - enum: 38 - qcom,glymur-smmu-500 39 - qcom,kaanapali-smmu-500 40 - qcom,milos-smmu-500 41 - qcom,qcm2290-smmu-500 42 - qcom,qcs615-smmu-500 43 - qcom,qcs8300-smmu-500 44 - qcom,qdu1000-smmu-500 45 - qcom,sa8255p-smmu-500 46 - qcom,sa8775p-smmu-500 47 - qcom,sar2130p-smmu-500 48 - qcom,sc7180-smmu-500 49 - qcom,sc7280-smmu-500 50 - qcom,sc8180x-smmu-500 51 - qcom,sc8280xp-smmu-500 52 - qcom,sdm670-smmu-500 53 - qcom,sdm845-smmu-500 54 - qcom,sdx55-smmu-500 55 - qcom,sdx65-smmu-500 56 - qcom,sdx75-smmu-500 57 - qcom,sm6115-smmu-500 58 - qcom,sm6125-smmu-500 59 - qcom,sm6350-smmu-500 60 - qcom,sm6375-smmu-500 61 - qcom,sm8150-smmu-500 62 - qcom,sm8250-smmu-500 63 - qcom,sm8350-smmu-500 64 - qcom,sm8450-smmu-500 65 - qcom,sm8550-smmu-500 66 - qcom,sm8650-smmu-500 67 - qcom,sm8750-smmu-500 68 - qcom,x1e80100-smmu-500 69 - const: qcom,smmu-500 70 - const: arm,mmu-500 71 72 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 73 deprecated: true 74 items: 75 # Do not add additional SoC to this list. Instead use two previous lists. 76 - enum: 77 - qcom,qcm2290-smmu-500 78 - qcom,sc7180-smmu-500 79 - qcom,sc7280-smmu-500 80 - qcom,sc8180x-smmu-500 81 - qcom,sc8280xp-smmu-500 82 - qcom,sdm845-smmu-500 83 - qcom,sm6115-smmu-500 84 - qcom,sm6350-smmu-500 85 - qcom,sm6375-smmu-500 86 - qcom,sm8150-smmu-500 87 - qcom,sm8250-smmu-500 88 - qcom,sm8350-smmu-500 89 - qcom,sm8450-smmu-500 90 - const: arm,mmu-500 91 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 92 items: 93 - enum: 94 - qcom,glymur-smmu-500 95 - qcom,kaanapali-smmu-500 96 - qcom,milos-smmu-500 97 - qcom,qcm2290-smmu-500 98 - qcom,qcs615-smmu-500 99 - qcom,qcs8300-smmu-500 100 - qcom,sa8255p-smmu-500 101 - qcom,sa8775p-smmu-500 102 - qcom,sar2130p-smmu-500 103 - qcom,sc7280-smmu-500 104 - qcom,sc8180x-smmu-500 105 - qcom,sc8280xp-smmu-500 106 - qcom,sm6115-smmu-500 107 - qcom,sm6125-smmu-500 108 - qcom,sm8150-smmu-500 109 - qcom,sm8250-smmu-500 110 - qcom,sm8350-smmu-500 111 - qcom,sm8450-smmu-500 112 - qcom,sm8550-smmu-500 113 - qcom,sm8650-smmu-500 114 - qcom,sm8750-smmu-500 115 - qcom,x1e80100-smmu-500 116 - const: qcom,adreno-smmu 117 - const: qcom,smmu-500 118 - const: arm,mmu-500 119 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 120 deprecated: true 121 items: 122 # Do not add additional SoC to this list. Instead use previous list. 123 - enum: 124 - qcom,sc7280-smmu-500 125 - qcom,sm8150-smmu-500 126 - qcom,sm8250-smmu-500 127 - const: qcom,adreno-smmu 128 - const: arm,mmu-500 129 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 130 items: 131 - enum: 132 - qcom,msm8996-smmu-v2 133 - qcom,sc7180-smmu-v2 134 - qcom,sdm630-smmu-v2 135 - qcom,sdm670-smmu-v2 136 - qcom,sdm845-smmu-v2 137 - qcom,sm6350-smmu-v2 138 - qcom,sm7150-smmu-v2 139 - const: qcom,adreno-smmu 140 - const: qcom,smmu-v2 141 - description: Marvell SoCs implementing "arm,mmu-500" 142 items: 143 - const: marvell,ap806-smmu-500 144 - const: arm,mmu-500 145 - description: NVIDIA SoCs that require memory controller interaction 146 and may program multiple ARM MMU-500s identically with the memory 147 controller interleaving translations between multiple instances 148 for improved performance. 149 items: 150 - enum: 151 - nvidia,tegra186-smmu 152 - nvidia,tegra194-smmu 153 - nvidia,tegra234-smmu 154 - const: nvidia,smmu-500 155 - items: 156 - const: arm,mmu-500 157 - const: arm,smmu-v2 158 - items: 159 - enum: 160 - arm,mmu-400 161 - arm,mmu-401 162 - const: arm,smmu-v1 163 - enum: 164 - arm,smmu-v1 165 - arm,smmu-v2 166 - arm,mmu-400 167 - arm,mmu-401 168 - arm,mmu-500 169 - cavium,smmu-v2 170 171 reg: 172 minItems: 1 173 maxItems: 2 174 175 '#global-interrupts': 176 description: The number of global interrupts exposed by the device. 177 $ref: /schemas/types.yaml#/definitions/uint32 178 minimum: 0 179 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 180 181 '#iommu-cells': 182 enum: [ 1, 2 ] 183 description: | 184 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 185 value of 1, each IOMMU specifier represents a distinct stream ID emitted 186 by that device into the relevant SMMU. 187 188 SMMUs with stream matching support and complex masters may use a value of 189 2, where the second cell of the IOMMU specifier represents an SMR mask to 190 combine with the ID in the first cell. Care must be taken to ensure the 191 set of matched IDs does not result in conflicts. 192 193 interrupts: 194 minItems: 1 195 maxItems: 388 # 260 plus 128 contexts 196 description: | 197 Interrupt list, with the first #global-interrupts entries corresponding to 198 the global interrupts and any following entries corresponding to context 199 interrupts, specified in order of their indexing by the SMMU. 200 201 For SMMUv2 implementations, there must be exactly one interrupt per 202 context bank. In the case of a single, combined interrupt, it must be 203 listed multiple times. 204 205 dma-coherent: 206 description: | 207 Present if page table walks made by the SMMU are cache coherent with the 208 CPU. 209 210 NOTE: this only applies to the SMMU itself, not masters connected 211 upstream of the SMMU. 212 213 calxeda,smmu-secure-config-access: 214 type: boolean 215 description: 216 Enable proper handling of buggy implementations that always use secure 217 access to SMMU configuration registers. In this case non-secure aliases of 218 secure registers have to be used during SMMU configuration. 219 220 stream-match-mask: 221 $ref: /schemas/types.yaml#/definitions/uint32 222 description: | 223 For SMMUs supporting stream matching and using #iommu-cells = <1>, 224 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 225 be programmed into the SMRn.MASK field of every stream match register 226 used). For cases where it is desirable to ignore some portion of every 227 Stream ID (e.g. for certain MMU-500 configurations given globally unique 228 input IDs). This property is not valid for SMMUs using stream indexing, or 229 using stream matching with #iommu-cells = <2>, and may be ignored if 230 present in such cases. 231 232 clock-names: 233 minItems: 1 234 maxItems: 7 235 236 clocks: 237 minItems: 1 238 maxItems: 7 239 240 power-domains: 241 minItems: 1 242 maxItems: 3 243 244 nvidia,memory-controller: 245 description: | 246 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 247 The memory controller needs to be programmed with a mapping of memory 248 client IDs to ARM SMMU stream IDs. 249 250 If this property is absent, the mapping programmed by early firmware 251 will be used and it is not guaranteed that IOMMU translations will be 252 enabled for any given device. 253 $ref: /schemas/types.yaml#/definitions/phandle 254 255required: 256 - compatible 257 - reg 258 - '#global-interrupts' 259 - '#iommu-cells' 260 - interrupts 261 262additionalProperties: false 263 264allOf: 265 - if: 266 properties: 267 compatible: 268 contains: 269 enum: 270 - nvidia,tegra186-smmu 271 - nvidia,tegra194-smmu 272 - nvidia,tegra234-smmu 273 then: 274 properties: 275 reg: 276 minItems: 1 277 maxItems: 2 278 279 # The reference to the memory controller is required to ensure that the 280 # memory client to stream ID mapping can be done synchronously with the 281 # IOMMU attachment. 282 required: 283 - nvidia,memory-controller 284 else: 285 properties: 286 reg: 287 maxItems: 1 288 289 - if: 290 properties: 291 compatible: 292 contains: 293 enum: 294 - qcom,msm8998-smmu-v2 295 - qcom,sdm630-smmu-v2 296 then: 297 anyOf: 298 - properties: 299 clock-names: 300 items: 301 - const: bus 302 clocks: 303 items: 304 - description: bus clock required for downstream bus access and for 305 the smmu ptw 306 - properties: 307 clock-names: 308 items: 309 - const: iface 310 - const: mem 311 - const: mem_iface 312 clocks: 313 items: 314 - description: interface clock required to access smmu's registers 315 through the TCU's programming interface. 316 - description: bus clock required for memory access 317 - description: bus clock required for GPU memory access 318 - properties: 319 clock-names: 320 items: 321 - const: iface-mm 322 - const: iface-smmu 323 - const: bus-smmu 324 clocks: 325 items: 326 - description: interface clock required to access mnoc's registers 327 through the TCU's programming interface. 328 - description: interface clock required to access smmu's registers 329 through the TCU's programming interface. 330 - description: bus clock required for the smmu ptw 331 332 - if: 333 properties: 334 compatible: 335 contains: 336 enum: 337 - qcom,sm6375-smmu-v2 338 then: 339 anyOf: 340 - properties: 341 clock-names: 342 items: 343 - const: bus 344 clocks: 345 items: 346 - description: bus clock required for downstream bus access and for 347 the smmu ptw 348 - properties: 349 clock-names: 350 items: 351 - const: iface 352 - const: mem 353 - const: mem_iface 354 clocks: 355 items: 356 - description: interface clock required to access smmu's registers 357 through the TCU's programming interface. 358 - description: bus clock required for memory access 359 - description: bus clock required for GPU memory access 360 - properties: 361 clock-names: 362 items: 363 - const: iface-mm 364 - const: iface-smmu 365 - const: bus-mm 366 - const: bus-smmu 367 clocks: 368 items: 369 - description: interface clock required to access mnoc's registers 370 through the TCU's programming interface. 371 - description: interface clock required to access smmu's registers 372 through the TCU's programming interface. 373 - description: bus clock required for downstream bus access 374 - description: bus clock required for the smmu ptw 375 376 - if: 377 properties: 378 compatible: 379 contains: 380 enum: 381 - qcom,msm8996-smmu-v2 382 - qcom,sc7180-smmu-v2 383 - qcom,sdm845-smmu-v2 384 then: 385 properties: 386 clock-names: 387 items: 388 - const: bus 389 - const: iface 390 391 clocks: 392 items: 393 - description: bus clock required for downstream bus access and for 394 the smmu ptw 395 - description: interface clock required to access smmu's registers 396 through the TCU's programming interface. 397 398 - if: 399 properties: 400 compatible: 401 contains: 402 enum: 403 - qcom,qcs8300-smmu-500 404 - qcom,sa8775p-smmu-500 405 - qcom,sc7280-smmu-500 406 - qcom,sc8280xp-smmu-500 407 then: 408 properties: 409 clock-names: 410 items: 411 - const: gcc_gpu_memnoc_gfx_clk 412 - const: gcc_gpu_snoc_dvm_gfx_clk 413 - const: gpu_cc_ahb_clk 414 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 415 - const: gpu_cc_cx_gmu_clk 416 - const: gpu_cc_hub_cx_int_clk 417 - const: gpu_cc_hub_aon_clk 418 419 clocks: 420 items: 421 - description: GPU memnoc_gfx clock 422 - description: GPU snoc_dvm_gfx clock 423 - description: GPU ahb clock 424 - description: GPU hlos1_vote_GPU smmu clock 425 - description: GPU cx_gmu clock 426 - description: GPU hub_cx_int clock 427 - description: GPU hub_aon clock 428 429 - if: 430 properties: 431 compatible: 432 contains: 433 enum: 434 - qcom,sc8180x-smmu-500 435 - qcom,sm6350-smmu-v2 436 - qcom,sm7150-smmu-v2 437 - qcom,sm8150-smmu-500 438 - qcom,sm8250-smmu-500 439 then: 440 properties: 441 clock-names: 442 items: 443 - const: ahb 444 - const: bus 445 - const: iface 446 447 clocks: 448 items: 449 - description: bus clock required for AHB bus access 450 - description: bus clock required for downstream bus access and for 451 the smmu ptw 452 - description: interface clock required to access smmu's registers 453 through the TCU's programming interface. 454 455 - if: 456 properties: 457 compatible: 458 items: 459 - enum: 460 - qcom,sm8350-smmu-500 461 - const: qcom,adreno-smmu 462 - const: qcom,smmu-500 463 - const: arm,mmu-500 464 then: 465 properties: 466 clock-names: 467 items: 468 - const: bus 469 - const: iface 470 - const: ahb 471 - const: hlos1_vote_gpu_smmu 472 - const: cx_gmu 473 - const: hub_cx_int 474 - const: hub_aon 475 clocks: 476 minItems: 7 477 maxItems: 7 478 479 - if: 480 properties: 481 compatible: 482 items: 483 - enum: 484 - qcom,qcm2290-smmu-500 485 - qcom,qcs615-smmu-500 486 - qcom,sm6115-smmu-500 487 - qcom,sm6125-smmu-500 488 - const: qcom,adreno-smmu 489 - const: qcom,smmu-500 490 - const: arm,mmu-500 491 then: 492 properties: 493 clock-names: 494 items: 495 - const: mem 496 - const: hlos 497 - const: iface 498 499 clocks: 500 items: 501 - description: GPU memory bus clock 502 - description: Voter clock required for HLOS SMMU access 503 - description: Interface clock required for register access 504 505 - if: 506 properties: 507 compatible: 508 items: 509 - const: qcom,sm8450-smmu-500 510 - const: qcom,adreno-smmu 511 - const: qcom,smmu-500 512 - const: arm,mmu-500 513 514 then: 515 properties: 516 clock-names: 517 items: 518 - const: gmu 519 - const: hub 520 - const: hlos 521 - const: bus 522 - const: iface 523 - const: ahb 524 525 clocks: 526 items: 527 - description: GMU clock 528 - description: GPU HUB clock 529 - description: HLOS vote clock 530 - description: GPU memory bus clock 531 - description: GPU SNoC bus clock 532 - description: GPU AHB clock 533 534 - if: 535 properties: 536 compatible: 537 items: 538 - enum: 539 - qcom,milos-smmu-500 540 - qcom,sar2130p-smmu-500 541 - qcom,sm8550-smmu-500 542 - qcom,sm8650-smmu-500 543 - qcom,x1e80100-smmu-500 544 - const: qcom,adreno-smmu 545 - const: qcom,smmu-500 546 - const: arm,mmu-500 547 then: 548 properties: 549 clock-names: 550 items: 551 - const: hlos 552 - const: bus 553 - const: iface 554 - const: ahb 555 556 clocks: 557 items: 558 - description: HLOS vote clock 559 - description: GPU memory bus clock 560 - description: GPU SNoC bus clock 561 - description: GPU AHB clock 562 563 - if: 564 properties: 565 compatible: 566 items: 567 - const: qcom,sm8750-smmu-500 568 - const: qcom,adreno-smmu 569 - const: qcom,smmu-500 570 - const: arm,mmu-500 571 then: 572 properties: 573 clock-names: 574 items: 575 - const: hlos 576 clocks: 577 items: 578 - description: HLOS vote clock 579 580 # Disallow clocks for all other platforms with specific compatibles 581 - if: 582 properties: 583 compatible: 584 contains: 585 enum: 586 - cavium,smmu-v2 587 - marvell,ap806-smmu-500 588 - nvidia,smmu-500 589 - qcom,qdu1000-smmu-500 590 - qcom,sa8255p-smmu-500 591 - qcom,sc7180-smmu-500 592 - qcom,sdm670-smmu-500 593 - qcom,sdm845-smmu-500 594 - qcom,sdx55-smmu-500 595 - qcom,sdx65-smmu-500 596 - qcom,sm6350-smmu-500 597 - qcom,sm6375-smmu-500 598 then: 599 properties: 600 clock-names: false 601 clocks: false 602 603 - if: 604 properties: 605 compatible: 606 contains: 607 const: qcom,sm6375-smmu-500 608 then: 609 properties: 610 power-domains: 611 items: 612 - description: SNoC MMU TBU RT GDSC 613 - description: SNoC MMU TBU NRT GDSC 614 - description: SNoC TURING MMU TBU0 GDSC 615 616 required: 617 - power-domains 618 else: 619 properties: 620 power-domains: 621 maxItems: 1 622 623examples: 624 - |+ 625 /* SMMU with stream matching or stream indexing */ 626 smmu1: iommu@ba5e0000 { 627 compatible = "arm,smmu-v1"; 628 reg = <0xba5e0000 0x10000>; 629 #global-interrupts = <2>; 630 interrupts = <0 32 4>, 631 <0 33 4>, 632 <0 34 4>, /* This is the first context interrupt */ 633 <0 35 4>, 634 <0 36 4>, 635 <0 37 4>; 636 #iommu-cells = <1>; 637 }; 638 639 /* device with two stream IDs, 0 and 7 */ 640 master1 { 641 iommus = <&smmu1 0>, 642 <&smmu1 7>; 643 }; 644 645 /* SMMU with stream matching */ 646 smmu2: iommu@ba5f0000 { 647 compatible = "arm,smmu-v1"; 648 reg = <0xba5f0000 0x10000>; 649 #global-interrupts = <2>; 650 interrupts = <0 38 4>, 651 <0 39 4>, 652 <0 40 4>, /* This is the first context interrupt */ 653 <0 41 4>, 654 <0 42 4>, 655 <0 43 4>; 656 #iommu-cells = <2>; 657 }; 658 659 /* device with stream IDs 0 and 7 */ 660 master2 { 661 iommus = <&smmu2 0 0>, 662 <&smmu2 7 0>; 663 }; 664 665 /* device with stream IDs 1, 17, 33 and 49 */ 666 master3 { 667 iommus = <&smmu2 1 0x30>; 668 }; 669 670 /* ARM MMU-500 with 10-bit stream ID input configuration */ 671 smmu3: iommu@ba600000 { 672 compatible = "arm,mmu-500", "arm,smmu-v2"; 673 reg = <0xba600000 0x10000>; 674 #global-interrupts = <2>; 675 interrupts = <0 44 4>, 676 <0 45 4>, 677 <0 46 4>, /* This is the first context interrupt */ 678 <0 47 4>, 679 <0 48 4>, 680 <0 49 4>; 681 #iommu-cells = <1>; 682 /* always ignore appended 5-bit TBU number */ 683 stream-match-mask = <0x7c00>; 684 }; 685 686 bus { 687 /* bus whose child devices emit one unique 10-bit stream 688 ID each, but may master through multiple SMMU TBUs */ 689 iommu-map = <0 &smmu3 0 0x400>; 690 }; 691 692 - |+ 693 /* Qcom's arm,smmu-v2 implementation */ 694 #include <dt-bindings/interrupt-controller/arm-gic.h> 695 #include <dt-bindings/interrupt-controller/irq.h> 696 smmu4: iommu@d00000 { 697 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 698 reg = <0xd00000 0x10000>; 699 700 #global-interrupts = <1>; 701 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 704 #iommu-cells = <1>; 705 power-domains = <&mmcc 0>; 706 707 clocks = <&mmcc 123>, 708 <&mmcc 124>; 709 clock-names = "bus", "iface"; 710 };
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