thead,c900-aclint-sswi.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ACLINT Supervisor-level Software Interrupt Device
  8
  9maintainers:
 10  - Inochi Amaoto <inochiama@outlook.com>
 11
 12description:
 13  The SSWI device is a part of the ACLINT device. It provides
 14  supervisor-level IPI functionality for a set of HARTs on a supported
 15  platforms. It provides a register to set an IPI (SETSSIP) for each
 16  HART connected to the SSWI device. See draft specification
 17  https://github.com/riscvarchive/riscv-aclint
 18
 19  Following variants of the SSWI ACLINT supported, using dedicated
 20  compatible string
 21  - THEAD C900
 22  - MIPS P8700
 23
 24properties:
 25  compatible:
 26    oneOf:
 27      - items:
 28          - enum:
 29              - sophgo,sg2044-aclint-sswi
 30          - const: thead,c900-aclint-sswi
 31      - items:
 32          - const: mips,p8700-aclint-sswi
 33      - items:
 34          - enum:
 35              - anlogic,dr1v90-aclint-sswi
 36          - const: nuclei,ux900-aclint-sswi
 37
 38  reg:
 39    maxItems: 1
 40
 41  "#interrupt-cells":
 42    const: 0
 43
 44  interrupt-controller: true
 45
 46  interrupts-extended:
 47    minItems: 1
 48    maxItems: 4095
 49
 50  riscv,hart-indexes:
 51    $ref: /schemas/types.yaml#/definitions/uint32-array
 52    minItems: 1
 53    maxItems: 4095
 54    description:
 55      A list of hart indexes that APLIC should use to address each hart
 56      that is mentioned in the "interrupts-extended"
 57
 58additionalProperties: false
 59
 60required:
 61  - compatible
 62  - reg
 63  - "#interrupt-cells"
 64  - interrupt-controller
 65  - interrupts-extended
 66
 67allOf:
 68  - if:
 69      properties:
 70        compatible:
 71          contains:
 72            const: mips,p8700-aclint-sswi
 73    then:
 74      required:
 75        - riscv,hart-indexes
 76    else:
 77      properties:
 78        riscv,hart-indexes: false
 79
 80examples:
 81  - |
 82    //Example 1
 83    interrupt-controller@94000000 {
 84      compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
 85      reg = <0x94000000 0x00004000>;
 86      #interrupt-cells = <0>;
 87      interrupt-controller;
 88      interrupts-extended = <&cpu1intc 1>,
 89                            <&cpu2intc 1>,
 90                            <&cpu3intc 1>,
 91                            <&cpu4intc 1>;
 92    };
 93
 94  - |
 95    //Example 2
 96    interrupt-controller@94000000 {
 97      compatible = "mips,p8700-aclint-sswi";
 98      reg = <0x94000000 0x00004000>;
 99      #interrupt-cells = <0>;
100      interrupt-controller;
101      interrupts-extended = <&cpu1intc 1>,
102                            <&cpu2intc 1>,
103                            <&cpu3intc 1>,
104                            <&cpu4intc 1>;
105      riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
106    };
107
108...