sifive,plic-1.0.0.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2# Copyright (C) 2020 SiFive, Inc.
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: SiFive Platform-Level Interrupt Controller (PLIC)
  9
 10description:
 11  SiFive SoCs and other RISC-V SoCs include an implementation of the
 12  Platform-Level Interrupt Controller (PLIC) high-level specification in
 13  the RISC-V Privileged Architecture specification. The PLIC connects all
 14  external interrupts in the system to all hart contexts in the system, via
 15  the external interrupt source in each hart.
 16
 17  A hart context is a privilege mode in a hardware execution thread. For example,
 18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
 19  privilege modes per hart; machine mode and supervisor mode.
 20
 21  Each interrupt can be enabled on per-context basis. Any context can claim
 22  a pending enabled interrupt and then release it once it has been handled.
 23
 24  Each interrupt has a configurable priority. Higher priority interrupts are
 25  serviced first.  Each context can specify a priority threshold. Interrupts
 26  with priority below this threshold will not cause the PLIC to raise its
 27  interrupt line leading to the context.
 28
 29  The PLIC supports both edge-triggered and level-triggered interrupts. For
 30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
 31  seen while an interrupt handler is active; the PLIC may either queue them or
 32  ignore them. In the first case, handlers are oblivious to the trigger type, so
 33  it is not included in the interrupt specifier. In the second case, software
 34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
 35  missing interrupts. This special handling is needed by at least the Renesas
 36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
 37
 38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
 39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
 40  contains a specific memory layout, which is documented in chapter 8 of the
 41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 42
 43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
 44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
 45  from S-mode. So add thead,c900-plic to distinguish them.
 46
 47maintainers:
 48  - Paul Walmsley  <paul.walmsley@sifive.com>
 49  - Palmer Dabbelt <palmer@dabbelt.com>
 50
 51properties:
 52  compatible:
 53    oneOf:
 54      - items:
 55          - enum:
 56              - andestech,qilai-plic
 57              - renesas,r9a07g043-plic
 58          - const: andestech,nceplic100
 59      - items:
 60          - enum:
 61              - anlogic,dr1v90-plic
 62              - canaan,k210-plic
 63              - eswin,eic7700-plic
 64              - microchip,pic64gx-plic
 65              - sifive,fu540-c000-plic
 66              - spacemit,k1-plic
 67              - starfive,jh7100-plic
 68              - starfive,jh7110-plic
 69              - tenstorrent,blackhole-plic
 70          - const: sifive,plic-1.0.0
 71      - items:
 72          - enum:
 73              - allwinner,sun20i-d1-plic
 74              - sophgo,cv1800b-plic
 75              - sophgo,cv1812h-plic
 76              - sophgo,sg2002-plic
 77              - sophgo,sg2042-plic
 78              - sophgo,sg2044-plic
 79              - thead,th1520-plic
 80          - const: thead,c900-plic
 81      - items:
 82          - const: ultrarisc,dp1000-plic
 83          - const: ultrarisc,cp100-plic
 84      - items:
 85          - const: sifive,plic-1.0.0
 86          - const: riscv,plic0
 87        deprecated: true
 88        description: For the QEMU virt machine only
 89
 90  reg:
 91    maxItems: 1
 92
 93  '#address-cells':
 94    const: 0
 95
 96  '#interrupt-cells': true
 97
 98  interrupt-controller: true
 99
100  interrupts-extended:
101    minItems: 1
102    maxItems: 15872
103    description:
104      Specifies which contexts are connected to the PLIC, with "-1" specifying
105      that a context is not present. Each node pointed to should be a
106      riscv,cpu-intc node, which has a riscv node as parent.
107
108  riscv,ndev:
109    $ref: /schemas/types.yaml#/definitions/uint32
110    description:
111      Specifies how many external interrupts are supported by this controller.
112
113  clocks: true
114
115  power-domains: true
116
117  resets: true
118
119required:
120  - compatible
121  - '#address-cells'
122  - '#interrupt-cells'
123  - interrupt-controller
124  - reg
125  - interrupts-extended
126  - riscv,ndev
127
128allOf:
129  - if:
130      properties:
131        compatible:
132          contains:
133            enum:
134              - andestech,nceplic100
135              - thead,c900-plic
136
137    then:
138      properties:
139        '#interrupt-cells':
140          const: 2
141
142    else:
143      properties:
144        '#interrupt-cells':
145          const: 1
146
147  - if:
148      properties:
149        compatible:
150          contains:
151            const: renesas,r9a07g043-plic
152
153    then:
154      properties:
155        clocks:
156          maxItems: 1
157
158        power-domains:
159          maxItems: 1
160
161        resets:
162          maxItems: 1
163
164      required:
165        - clocks
166        - power-domains
167        - resets
168
169additionalProperties: false
170
171examples:
172  - |
173    plic: interrupt-controller@c000000 {
174      #address-cells = <0>;
175      #interrupt-cells = <1>;
176      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
177      interrupt-controller;
178      interrupts-extended = <&cpu0_intc 11>,
179                            <&cpu1_intc 11>, <&cpu1_intc 9>,
180                            <&cpu2_intc 11>, <&cpu2_intc 9>,
181                            <&cpu3_intc 11>, <&cpu3_intc 9>,
182                            <&cpu4_intc 11>, <&cpu4_intc 9>;
183      reg = <0xc000000 0x4000000>;
184      riscv,ndev = <10>;
185    };