qcom,pdc.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: PDC interrupt controller
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description: |
 13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
 14  Power Domain Controller (PDC) that is on always-on domain. In addition to
 15  providing power control for the power domains, the hardware also has an
 16  interrupt controller that can be used to help detect edge low interrupts as
 17  well detect interrupts when the GIC is non-operational.
 18
 19  GIC is parent interrupt controller at the highest level. Platform interrupt
 20  controller PDC is next in hierarchy, followed by others. Drivers requiring
 21  wakeup capabilities of their device interrupts routed through the PDC, must
 22  specify PDC as their interrupt controller and request the PDC port associated
 23  with the GIC interrupt. See example below.
 24
 25properties:
 26  compatible:
 27    items:
 28      - enum:
 29          - qcom,glymur-pdc
 30          - qcom,qcs615-pdc
 31          - qcom,qcs8300-pdc
 32          - qcom,qdu1000-pdc
 33          - qcom,sa8255p-pdc
 34          - qcom,sa8775p-pdc
 35          - qcom,sar2130p-pdc
 36          - qcom,sc7180-pdc
 37          - qcom,sc7280-pdc
 38          - qcom,sc8180x-pdc
 39          - qcom,sc8280xp-pdc
 40          - qcom,sdm670-pdc
 41          - qcom,sdm845-pdc
 42          - qcom,sdx55-pdc
 43          - qcom,sdx65-pdc
 44          - qcom,sdx75-pdc
 45          - qcom,sm4450-pdc
 46          - qcom,sm6350-pdc
 47          - qcom,sm8150-pdc
 48          - qcom,sm8250-pdc
 49          - qcom,sm8350-pdc
 50          - qcom,sm8450-pdc
 51          - qcom,sm8550-pdc
 52          - qcom,sm8650-pdc
 53          - qcom,sm8750-pdc
 54          - qcom,x1e80100-pdc
 55      - const: qcom,pdc
 56
 57  reg:
 58    minItems: 1
 59    items:
 60      - description: PDC base register region
 61      - description: Edge or Level config register for SPI interrupts
 62
 63  '#interrupt-cells':
 64    const: 2
 65
 66  interrupt-controller: true
 67
 68  qcom,pdc-ranges:
 69    $ref: /schemas/types.yaml#/definitions/uint32-matrix
 70    minItems: 1
 71    maxItems: 128 # no hard limit
 72    items:
 73      items:
 74        - description: starting PDC port
 75        - description: GIC hwirq number for the PDC port
 76        - description: number of interrupts in sequence
 77    description: |
 78      Specifies the PDC pin offset and the number of PDC ports.
 79      The tuples indicates the valid mapping of valid PDC ports
 80      and their hwirq mapping.
 81
 82required:
 83  - compatible
 84  - reg
 85  - '#interrupt-cells'
 86  - interrupt-controller
 87  - qcom,pdc-ranges
 88
 89additionalProperties: false
 90
 91examples:
 92  - |
 93    #include <dt-bindings/interrupt-controller/irq.h>
 94
 95    pdc: interrupt-controller@b220000 {
 96        compatible = "qcom,sdm845-pdc", "qcom,pdc";
 97        reg = <0xb220000 0x30000>;
 98        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
 99        #interrupt-cells = <2>;
100        interrupt-parent = <&intc>;
101        interrupt-controller;
102    };
103
104    wake-device {
105        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
106    };