apple,aic2.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Apple Interrupt Controller 2
  8
  9maintainers:
 10  - Hector Martin <marcan@marcan.st>
 11
 12description: |
 13  The Apple Interrupt Controller 2 is a simple interrupt controller present on
 14  Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
 15
 16  It provides the following features:
 17
 18  - Level-triggered hardware IRQs wired to SoC blocks
 19    - Single mask bit per IRQ
 20    - Automatic masking on event delivery (auto-ack)
 21    - Software triggering (ORed with hw line)
 22  - Automatic prioritization (single event/ack register per CPU, lower IRQs =
 23    higher priority)
 24  - Automatic masking on ack
 25  - Support for multiple dies
 26
 27  This device also represents the FIQ interrupt sources on platforms using AIC,
 28  which do not go through a discrete interrupt controller. It also handles
 29  FIQ-based Fast IPIs.
 30
 31properties:
 32  compatible:
 33    items:
 34      - enum:
 35          - apple,t8112-aic
 36          - apple,t6000-aic
 37          - apple,t6020-aic
 38      - const: apple,aic2
 39
 40  interrupt-controller: true
 41
 42  '#interrupt-cells':
 43    minimum: 3
 44    maximum: 4
 45    description: |
 46      The 1st cell contains the interrupt type:
 47        - 0: Hardware IRQ
 48        - 1: FIQ
 49
 50      The 2nd cell contains the die ID (only present on apple,t6000-aic).
 51
 52      The next cell contains the interrupt number.
 53        - HW IRQs: interrupt number
 54        - FIQs:
 55          - 0: physical HV timer
 56          - 1: virtual HV timer
 57          - 2: physical guest timer
 58          - 3: virtual guest timer
 59
 60      The last cell contains the interrupt flags. This is normally
 61      IRQ_TYPE_LEVEL_HIGH (4).
 62
 63  reg:
 64    items:
 65      - description: Address and size of the main AIC2 registers.
 66      - description: Address and size of the AIC2 Event register.
 67
 68  reg-names:
 69    items:
 70      - const: core
 71      - const: event
 72
 73  power-domains:
 74    maxItems: 1
 75
 76  affinities:
 77    type: object
 78    additionalProperties: false
 79    description:
 80      FIQ affinity can be expressed as a single "affinities" node,
 81      containing a set of sub-nodes, one per FIQ with a non-default
 82      affinity.
 83    patternProperties:
 84      "^.+-affinity$":
 85        type: object
 86        additionalProperties: false
 87        properties:
 88          apple,fiq-index:
 89            description:
 90              The interrupt number specified as a FIQ, and for which
 91              the affinity is not the default.
 92            $ref: /schemas/types.yaml#/definitions/uint32
 93            maximum: 5
 94
 95          cpus:
 96            $ref: /schemas/types.yaml#/definitions/phandle-array
 97            description:
 98              Should be a list of phandles to CPU nodes (as described in
 99              Documentation/devicetree/bindings/arm/cpus.yaml).
100
101        required:
102          - apple,fiq-index
103          - cpus
104
105required:
106  - compatible
107  - '#interrupt-cells'
108  - interrupt-controller
109  - reg
110  - reg-names
111
112additionalProperties: false
113
114allOf:
115  - $ref: /schemas/interrupt-controller.yaml#
116  - if:
117      properties:
118        compatible:
119          contains:
120            const: apple,t8112-aic
121    then:
122      properties:
123        '#interrupt-cells':
124          const: 3
125    else:
126      properties:
127        '#interrupt-cells':
128          const: 4
129
130examples:
131  - |
132    soc {
133        #address-cells = <2>;
134        #size-cells = <2>;
135
136        aic: interrupt-controller@28e100000 {
137            compatible = "apple,t6000-aic", "apple,aic2";
138            #interrupt-cells = <4>;
139            interrupt-controller;
140            reg = <0x2 0x8e100000 0x0 0xc000>,
141                  <0x2 0x8e10c000 0x0 0x4>;
142            reg-names = "core", "event";
143        };
144    };