apple,aic.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Apple Interrupt Controller
  8
  9maintainers:
 10  - Hector Martin <marcan@marcan.st>
 11
 12description: |
 13  The Apple Interrupt Controller is a simple interrupt controller present on
 14  Apple ARM SoC platforms, including various iPhone and iPad devices and the
 15  "Apple Silicon" Macs.
 16
 17  It provides the following features:
 18
 19  - Level-triggered hardware IRQs wired to SoC blocks
 20    - Single mask bit per IRQ
 21    - Per-IRQ affinity setting
 22    - Automatic masking on event delivery (auto-ack)
 23    - Software triggering (ORed with hw line)
 24  - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
 25    if not symmetric)
 26  - Automatic prioritization (single event/ack register per CPU, lower IRQs =
 27    higher priority)
 28  - Automatic masking on ack
 29  - Default "this CPU" register view and explicit per-CPU views
 30
 31  This device also represents the FIQ interrupt sources on platforms using AIC,
 32  which do not go through a discrete interrupt controller.
 33
 34  IPIs may be performed via MMIO registers on all variants of AIC. Starting
 35  from A11, system registers may also be used for "fast" IPIs. Starting from
 36  M1, even faster IPIs within the same cluster may be achieved by writing to
 37  a "local" fast IPI register as opposed to using the "global" fast IPI
 38  register.
 39
 40allOf:
 41  - $ref: /schemas/interrupt-controller.yaml#
 42
 43properties:
 44  compatible:
 45    items:
 46      - enum:
 47          - apple,s5l8960x-aic
 48          - apple,t7000-aic
 49          - apple,s8000-aic
 50          - apple,t8010-aic
 51          - apple,t8015-aic
 52          - apple,t8103-aic
 53      - const: apple,aic
 54
 55  interrupt-controller: true
 56
 57  '#interrupt-cells':
 58    const: 3
 59    description: |
 60      The 1st cell contains the interrupt type:
 61        - 0: Hardware IRQ
 62        - 1: FIQ
 63
 64      The 2nd cell contains the interrupt number.
 65        - HW IRQs: interrupt number
 66        - FIQs:
 67          - 0: physical HV timer
 68          - 1: virtual HV timer
 69          - 2: physical guest timer
 70          - 3: virtual guest timer
 71          - 4: 'efficient' CPU PMU
 72          - 5: 'performance' CPU PMU
 73
 74      The 3rd cell contains the interrupt flags. This is normally
 75      IRQ_TYPE_LEVEL_HIGH (4).
 76
 77  reg:
 78    description: |
 79      Specifies base physical address and size of the AIC registers.
 80    maxItems: 1
 81
 82  power-domains:
 83    maxItems: 1
 84
 85  affinities:
 86    type: object
 87    additionalProperties: false
 88    description:
 89      FIQ affinity can be expressed as a single "affinities" node,
 90      containing a set of sub-nodes, one per FIQ with a non-default
 91      affinity.
 92    patternProperties:
 93      "^.+-affinity$":
 94        type: object
 95        additionalProperties: false
 96        properties:
 97          apple,fiq-index:
 98            description:
 99              The interrupt number specified as a FIQ, and for which
100              the affinity is not the default.
101            $ref: /schemas/types.yaml#/definitions/uint32
102            maximum: 5
103
104          cpus:
105            description:
106              Should be a list of phandles to CPU nodes (as described in
107              Documentation/devicetree/bindings/arm/cpus.yaml).
108
109        required:
110          - apple,fiq-index
111          - cpus
112
113required:
114  - compatible
115  - '#interrupt-cells'
116  - interrupt-controller
117  - reg
118
119additionalProperties: false
120
121examples:
122  - |
123    soc {
124        #address-cells = <2>;
125        #size-cells = <2>;
126
127        aic: interrupt-controller@23b100000 {
128            compatible = "apple,t8103-aic", "apple,aic";
129            #interrupt-cells = <3>;
130            interrupt-controller;
131            reg = <0x2 0x3b100000 0x0 0x8000>;
132        };
133    };