qcom,sm8550-rpmh.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550
  8
  9maintainers:
 10  - Abel Vesa <abel.vesa@linaro.org>
 11  - Neil Armstrong <neil.armstrong@linaro.org>
 12
 13description: |
 14  RPMh interconnect providers support system bandwidth requirements through
 15  RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
 16  able to communicate with the BCM through the Resource State Coordinator (RSC)
 17  associated with each execution environment. Provider nodes must point to at
 18  least one RPMh device child node pertaining to their RSC and each provider
 19  can map to multiple RPMh resources.
 20
 21  See also: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h
 22
 23properties:
 24  compatible:
 25    enum:
 26      - qcom,sm8550-aggre1-noc
 27      - qcom,sm8550-aggre2-noc
 28      - qcom,sm8550-clk-virt
 29      - qcom,sm8550-cnoc-main
 30      - qcom,sm8550-config-noc
 31      - qcom,sm8550-gem-noc
 32      - qcom,sm8550-lpass-ag-noc
 33      - qcom,sm8550-lpass-lpiaon-noc
 34      - qcom,sm8550-lpass-lpicx-noc
 35      - qcom,sm8550-mc-virt
 36      - qcom,sm8550-mmss-noc
 37      - qcom,sm8550-nsp-noc
 38      - qcom,sm8550-pcie-anoc
 39      - qcom,sm8550-system-noc
 40
 41  reg:
 42    maxItems: 1
 43
 44  clocks:
 45    minItems: 1
 46    maxItems: 2
 47
 48allOf:
 49  - $ref: qcom,rpmh-common.yaml#
 50  - if:
 51      properties:
 52        compatible:
 53          contains:
 54            enum:
 55              - qcom,sm8550-clk-virt
 56              - qcom,sm8550-mc-virt
 57    then:
 58      properties:
 59        reg: false
 60    else:
 61      required:
 62        - reg
 63
 64  - if:
 65      properties:
 66        compatible:
 67          contains:
 68            enum:
 69              - qcom,sm8550-pcie-anoc
 70    then:
 71      properties:
 72        clocks:
 73          items:
 74            - description: aggre-NOC PCIe AXI clock
 75            - description: cfg-NOC PCIe a-NOC AHB clock
 76
 77  - if:
 78      properties:
 79        compatible:
 80          contains:
 81            enum:
 82              - qcom,sm8550-aggre1-noc
 83    then:
 84      properties:
 85        clocks:
 86          items:
 87            - description: aggre UFS PHY AXI clock
 88            - description: aggre USB3 PRIM AXI clock
 89
 90  - if:
 91      properties:
 92        compatible:
 93          contains:
 94            enum:
 95              - qcom,sm8550-aggre2-noc
 96    then:
 97      properties:
 98        clocks:
 99          items:
100            - description: RPMH CC IPA clock
101
102  - if:
103      properties:
104        compatible:
105          contains:
106            enum:
107              - qcom,sm8550-aggre1-noc
108              - qcom,sm8550-aggre2-noc
109              - qcom,sm8550-pcie-anoc
110    then:
111      required:
112        - clocks
113    else:
114      properties:
115        clocks: false
116
117required:
118  - compatible
119
120unevaluatedProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
125
126    clk_virt: interconnect-0 {
127      compatible = "qcom,sm8550-clk-virt";
128      #interconnect-cells = <2>;
129      qcom,bcm-voters = <&apps_bcm_voter>;
130    };
131
132    aggre1_noc: interconnect@16e0000 {
133      compatible = "qcom,sm8550-aggre1-noc";
134      reg = <0x016e0000 0x14400>;
135      #interconnect-cells = <2>;
136      clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
137               <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
138      qcom,bcm-voters = <&apps_bcm_voter>;
139    };