st,stm32-adc.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STMicroelectronics STM32 ADC
  8
  9description: |
 10  STM32 ADC is a successive approximation analog-to-digital converter.
 11  It has several multiplexed input channels. Conversions can be performed
 12  in single, continuous, scan or discontinuous mode. Result of the ADC is
 13  stored in a left-aligned or right-aligned 32-bit data register.
 14  Conversions can be launched in software or using hardware triggers.
 15
 16  The analog watchdog feature allows the application to detect if the input
 17  voltage goes beyond the user-defined, higher or lower thresholds.
 18
 19  Each STM32 ADC block can have up to 3 ADC instances.
 20
 21maintainers:
 22  - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
 23
 24properties:
 25  compatible:
 26    enum:
 27      - st,stm32f4-adc-core
 28      - st,stm32h7-adc-core
 29      - st,stm32mp1-adc-core
 30      - st,stm32mp13-adc-core
 31
 32  reg:
 33    maxItems: 1
 34
 35  interrupts:
 36    description: |
 37      One or more interrupts for ADC block, depending on part used:
 38        - stm32f4 and stm32h7 share a common ADC interrupt line.
 39        - stm32mp1 has two separate interrupt lines, one for each ADC within
 40          ADC block.
 41        - stm32mp13 has an interrupt line per ADC block.
 42    minItems: 1
 43    maxItems: 2
 44
 45  clocks:
 46    minItems: 1
 47    maxItems: 2
 48    description: |
 49      Core can use up to two clocks, depending on part used:
 50        - "adc" clock: for the analog circuitry, common to all ADCs.
 51          It's required on stm32f4.
 52          It's optional on stm32h7 and stm32mp1.
 53        - "bus" clock: for registers access, common to all ADCs.
 54          It's not present on stm32f4.
 55          It's required on stm32h7 and stm32mp1.
 56
 57  clock-names:
 58    minItems: 1
 59    maxItems: 2
 60
 61  st,max-clk-rate-hz:
 62    description:
 63      Allow to specify desired max clock rate used by analog circuitry.
 64
 65  vdda-supply:
 66    description: Phandle to the vdda input analog voltage.
 67
 68  vref-supply:
 69    description: Phandle to the vref input analog reference voltage.
 70
 71  booster-supply:
 72    description:
 73      Phandle to the embedded booster regulator that can be used to supply ADC
 74      analog input switches on stm32h7 and stm32mp1.
 75
 76  vdd-supply:
 77    description:
 78      Phandle to the vdd input voltage. It can be used to supply ADC analog
 79      input switches on stm32mp1.
 80
 81  st,syscfg:
 82    description:
 83      Phandle to system configuration controller. It can be used to control the
 84      analog circuitry on stm32mp1.
 85    $ref: /schemas/types.yaml#/definitions/phandle-array
 86
 87  interrupt-controller: true
 88
 89  '#interrupt-cells':
 90    const: 1
 91
 92  '#address-cells':
 93    const: 1
 94
 95  '#size-cells':
 96    const: 0
 97
 98  access-controllers:
 99    minItems: 1
100    maxItems: 2
101
102allOf:
103  - if:
104      properties:
105        compatible:
106          contains:
107            const: st,stm32f4-adc-core
108
109    then:
110      properties:
111        clocks:
112          maxItems: 1
113
114        clock-names:
115          const: adc
116
117        interrupts:
118          items:
119            - description: interrupt line common for all ADCs
120
121        st,max-clk-rate-hz:
122          minimum: 600000
123          maximum: 36000000
124          default: 36000000
125
126        booster-supply: false
127
128        vdd-supply: false
129
130        st,syscfg: false
131
132  - if:
133      properties:
134        compatible:
135          contains:
136            const: st,stm32h7-adc-core
137
138    then:
139      properties:
140        clocks:
141          minItems: 1
142          maxItems: 2
143
144        clock-names:
145          items:
146            - const: bus
147            - const: adc
148          minItems: 1
149
150        interrupts:
151          items:
152            - description: interrupt line common for all ADCs
153
154        st,max-clk-rate-hz:
155          minimum: 120000
156          maximum: 36000000
157          default: 36000000
158
159        vdd-supply: false
160
161        st,syscfg: false
162
163  - if:
164      properties:
165        compatible:
166          contains:
167            const: st,stm32mp1-adc-core
168
169    then:
170      properties:
171        clocks:
172          minItems: 1
173          maxItems: 2
174
175        clock-names:
176          items:
177            - const: bus
178            - const: adc
179          minItems: 1
180
181        interrupts:
182          items:
183            - description: interrupt line for ADC1
184            - description: interrupt line for ADC2
185
186        st,max-clk-rate-hz:
187          minimum: 120000
188          maximum: 36000000
189          default: 36000000
190
191  - if:
192      properties:
193        compatible:
194          contains:
195            const: st,stm32mp13-adc-core
196
197    then:
198      properties:
199        clocks:
200          minItems: 1
201          maxItems: 2
202
203        clock-names:
204          items:
205            - const: bus
206            - const: adc
207          minItems: 1
208
209        interrupts:
210          items:
211            - description: ADC interrupt line
212
213        st,max-clk-rate-hz:
214          minimum: 150000
215          maximum: 75000000
216          default: 75000000
217
218additionalProperties: false
219
220required:
221  - compatible
222  - reg
223  - interrupts
224  - clocks
225  - clock-names
226  - vdda-supply
227  - vref-supply
228  - interrupt-controller
229  - '#interrupt-cells'
230  - '#address-cells'
231  - '#size-cells'
232
233patternProperties:
234  "^adc@[0-9]+$":
235    type: object
236    description:
237      An ADC block node should contain at least one subnode, representing an
238      ADC instance available on the machine.
239
240    properties:
241      compatible:
242        enum:
243          - st,stm32f4-adc
244          - st,stm32h7-adc
245          - st,stm32mp1-adc
246          - st,stm32mp13-adc
247
248      reg:
249        description: |
250          Offset of ADC instance in ADC block. Valid values are:
251            - 0x0:   ADC1
252            - 0x100: ADC2
253            - 0x200: ADC3 (stm32f4 only)
254        maxItems: 1
255
256      '#io-channel-cells':
257        const: 1
258
259      '#address-cells':
260        const: 1
261
262      '#size-cells':
263        const: 0
264
265      interrupts:
266        description: |
267          IRQ Line for the ADC instance. Valid values are:
268            - 0 for adc@0 (single adc for stm32mp13)
269            - 1 for adc@100
270            - 2 for adc@200 (stm32f4 only)
271        maxItems: 1
272
273      clocks:
274        description:
275          Input clock private to this ADC instance. It's required only on
276          stm32f4, that has per instance clock input for registers access.
277        maxItems: 1
278
279      dmas:
280        description: RX DMA Channel
281        maxItems: 1
282
283      dma-names:
284        const: rx
285
286      assigned-resolution-bits:
287        description: |
288          Resolution (bits) to use for conversions:
289            - can be 6, 8, 10 or 12 on stm32f4 and stm32mp13
290            - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
291
292      st,adc-channels:
293        description: |
294          List of single-ended channels muxed for this ADC. It can have up to:
295            - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
296            - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
297            - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
298              stm32mp1.
299        $ref: /schemas/types.yaml#/definitions/uint32-array
300        deprecated: true
301
302      st,adc-diff-channels:
303        description: |
304          List of differential channels muxed for this ADC. Some channels can
305          be configured as differential instead of single-ended on stm32h7 and
306          on stm32mp1. Positive and negative inputs pairs are listed:
307          <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
308
309          Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
310          required if no adc generic channel is defined. These legacy channel
311          properties are exclusive with adc generic channel bindings.
312          Both properties can be used together. Some channels can be
313          used as single-ended and some other ones as differential (mixed). But
314          channels can't be configured both as single-ended and differential.
315        $ref: /schemas/types.yaml#/definitions/uint32-matrix
316        items:
317          items:
318            - description: |
319                "vinp" indicates positive input number
320              minimum: 0
321              maximum: 19
322            - description: |
323                "vinn" indicates negative input number
324              minimum: 0
325              maximum: 19
326        deprecated: true
327
328      st,min-sample-time-nsecs:
329        description:
330          Minimum sampling time in nanoseconds. Depending on hardware (board)
331          e.g. high/low analog input source impedance, fine tune of ADC
332          sampling time may be recommended. This can be either one value or an
333          array that matches "st,adc-channels" and/or "st,adc-diff-channels"
334          list, to set sample time resp. for all channels, or independently for
335          each channel.
336        $ref: /schemas/types.yaml#/definitions/uint32-array
337        deprecated: true
338
339      nvmem-cells:
340        items:
341          - description: Phandle to the calibration vrefint data provided by otp
342
343      nvmem-cell-names:
344        items:
345          - const: vrefint
346
347    patternProperties:
348      "^channel@([0-9]|1[0-9])$":
349        type: object
350        $ref: adc.yaml
351        description: Represents the external channels which are connected to the ADC.
352
353        properties:
354          reg:
355            items:
356              minimum: 0
357              maximum: 19
358
359          label:
360            description: |
361              Unique name to identify which channel this is.
362              Reserved label names "vddcore", "vddcpu", "vddq_ddr", "vrefint" and "vbat"
363              are used to identify internal channels with matching names.
364
365          diff-channels:
366            $ref: /schemas/types.yaml#/definitions/uint32-array
367            items:
368              minimum: 0
369              maximum: 19
370
371          st,min-sample-time-ns:
372            description: |
373              Minimum sampling time in nanoseconds. Depending on hardware (board)
374              e.g. high/low analog input source impedance, fine tune of ADC
375              sampling time may be recommended.
376
377        required:
378          - reg
379
380        additionalProperties: false
381
382    allOf:
383      - if:
384          properties:
385            compatible:
386              contains:
387                const: st,stm32f4-adc
388
389        then:
390          properties:
391            reg:
392              enum:
393                - 0x0
394                - 0x100
395                - 0x200
396
397            interrupts:
398              minimum: 0
399              maximum: 2
400
401            assigned-resolution-bits:
402              enum: [6, 8, 10, 12]
403              default: 12
404
405            st,adc-channels:
406              minItems: 1
407              maxItems: 16
408              items:
409                minimum: 0
410                maximum: 15
411
412            st,adc-diff-channels: false
413
414            st,min-sample-time-nsecs:
415              minItems: 1
416              maxItems: 16
417              items:
418                minimum: 80
419
420          required:
421            - clocks
422
423      - if:
424          properties:
425            compatible:
426              contains:
427                enum:
428                  - st,stm32h7-adc
429                  - st,stm32mp1-adc
430
431        then:
432          properties:
433            reg:
434              enum:
435                - 0x0
436                - 0x100
437
438            interrupts:
439              minimum: 0
440              maximum: 1
441
442            assigned-resolution-bits:
443              enum: [8, 10, 12, 14, 16]
444              default: 16
445
446            st,adc-channels:
447              minItems: 1
448              maxItems: 20
449              items:
450                minimum: 0
451                maximum: 19
452
453            st,min-sample-time-nsecs:
454              minItems: 1
455              maxItems: 20
456              items:
457                minimum: 40
458
459      - if:
460          properties:
461            compatible:
462              contains:
463                const: st,stm32mp13-adc
464
465        then:
466          properties:
467            reg:
468              const: 0x0
469
470            interrupts:
471              const: 0
472
473            assigned-resolution-bits:
474              enum: [6, 8, 10, 12]
475              default: 12
476
477            st,adc-channels:
478              minItems: 1
479              maxItems: 19
480              items:
481                minimum: 0
482                maximum: 18
483
484            st,min-sample-time-nsecs:
485              minItems: 1
486              maxItems: 19
487              items:
488                minimum: 40
489    additionalProperties: false
490
491    required:
492      - compatible
493      - reg
494      - interrupts
495      - '#io-channel-cells'
496
497examples:
498  - |
499    // Example 1: with stm32f429, ADC1, single-ended channel 8
500    adc123: adc@40012000 {
501        compatible = "st,stm32f4-adc-core";
502        reg = <0x40012000 0x400>;
503        interrupts = <18>;
504        clocks = <&rcc 0 168>;
505        clock-names = "adc";
506        st,max-clk-rate-hz = <36000000>;
507        vdda-supply = <&vdda>;
508        vref-supply = <&vref>;
509        interrupt-controller;
510        #interrupt-cells = <1>;
511        #address-cells = <1>;
512        #size-cells = <0>;
513        adc@0 {
514            compatible = "st,stm32f4-adc";
515            #io-channel-cells = <1>;
516            reg = <0x0>;
517            clocks = <&rcc 0 168>;
518            interrupt-parent = <&adc123>;
519            interrupts = <0>;
520            st,adc-channels = <8>;
521            dmas = <&dma2 0 0 0x400 0x0>;
522            dma-names = "rx";
523            assigned-resolution-bits = <8>;
524        };
525        // ...
526        // other adc child nodes follow...
527    };
528
529  - |
530    // Example 2: with stm32mp157c to setup ADC1 with:
531    // - channels 0 & 1 as single-ended
532    // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
533    #include <dt-bindings/interrupt-controller/arm-gic.h>
534    #include <dt-bindings/clock/stm32mp1-clks.h>
535    adc12: adc@48003000 {
536        compatible = "st,stm32mp1-adc-core";
537        reg = <0x48003000 0x400>;
538        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
539                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
540        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
541        clock-names = "bus", "adc";
542        booster-supply = <&booster>;
543        vdd-supply = <&vdd>;
544        vdda-supply = <&vdda>;
545        vref-supply = <&vref>;
546        st,syscfg = <&syscfg>;
547        interrupt-controller;
548        #interrupt-cells = <1>;
549        #address-cells = <1>;
550        #size-cells = <0>;
551        adc@0 {
552            compatible = "st,stm32mp1-adc";
553            #io-channel-cells = <1>;
554            reg = <0x0>;
555            interrupt-parent = <&adc12>;
556            interrupts = <0>;
557            st,adc-channels = <0 1>;
558            st,adc-diff-channels = <2 6>, <3 7>;
559            st,min-sample-time-nsecs = <5000>;
560            dmas = <&dmamux1 9 0x400 0x05>;
561            dma-names = "rx";
562        };
563        // ...
564        // other adc child node follow...
565    };
566
567  - |
568    // Example 3: with stm32mp157c to setup ADC2 with:
569    // - internal channels 13, 14, 15.
570    #include <dt-bindings/interrupt-controller/arm-gic.h>
571    #include <dt-bindings/clock/stm32mp1-clks.h>
572    adc122: adc@48003000 {
573        compatible = "st,stm32mp1-adc-core";
574        reg = <0x48003000 0x400>;
575        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
576                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
577        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
578        clock-names = "bus", "adc";
579        booster-supply = <&booster>;
580        vdd-supply = <&vdd>;
581        vdda-supply = <&vdda>;
582        vref-supply = <&vref>;
583        st,syscfg = <&syscfg>;
584        interrupt-controller;
585        #interrupt-cells = <1>;
586        #address-cells = <1>;
587        #size-cells = <0>;
588        adc@100 {
589            compatible = "st,stm32mp1-adc";
590            #io-channel-cells = <1>;
591            reg = <0x100>;
592            interrupts = <1>;
593            #address-cells = <1>;
594            #size-cells = <0>;
595            channel@13 {
596                reg = <13>;
597                label = "vrefint";
598                st,min-sample-time-ns = <9000>;
599            };
600            channel@14 {
601                reg = <14>;
602                label = "vddcore";
603                st,min-sample-time-ns = <9000>;
604            };
605            channel@15 {
606                reg = <15>;
607                label = "vbat";
608                st,min-sample-time-ns = <9000>;
609            };
610        };
611    };
612
613...