renesas,rzn1-adc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas RZ/N1 Analog to Digital Converter (ADC)
  8
  9maintainers:
 10  - Herve Codina <herve.codina@bootlin.com>
 11
 12description:
 13  The Renesas RZ/N1 ADC controller available in the Renesas RZ/N1 SoCs family
 14  can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are
 15  handled through ADC controller virtual channels.
 16
 17properties:
 18  compatible:
 19    items:
 20      - const: renesas,r9a06g032-adc   # RZ/N1D
 21      - const: renesas,rzn1-adc
 22
 23  reg:
 24    maxItems: 1
 25
 26  clocks:
 27    items:
 28      - description: APB internal bus clock
 29      - description: ADC clock
 30
 31  clock-names:
 32    items:
 33      - const: pclk
 34      - const: adc
 35
 36  power-domains:
 37    maxItems: 1
 38
 39  adc1-avdd-supply:
 40    description:
 41      ADC1 analog power supply.
 42
 43  adc1-vref-supply:
 44    description:
 45      ADC1 reference voltage supply.
 46
 47  adc2-avdd-supply:
 48    description:
 49      ADC2 analog power supply.
 50
 51  adc2-vref-supply:
 52    description:
 53      ADC2 reference voltage supply.
 54
 55  '#io-channel-cells':
 56    const: 1
 57    description: |
 58      Channels numbers available:
 59        if ADC1 is used (i.e. adc1-{avdd,vref}-supply present):
 60          - 0: ADC1 IN0
 61          - 1: ADC1 IN1
 62          - 2: ADC1 IN2
 63          - 3: ADC1 IN3
 64          - 4: ADC1 IN4
 65          - 5: ADC1 IN6
 66          - 6: ADC1 IN7
 67          - 7: ADC1 IN8
 68        if ADC2 is used (i.e. adc2-{avdd,vref}-supply present):
 69          - 8: ADC2 IN0
 70          - 9: ADC2 IN1
 71          - 10: ADC2 IN2
 72          - 11: ADC2 IN3
 73          - 12: ADC2 IN4
 74          - 13: ADC2 IN6
 75          - 14: ADC2 IN7
 76          - 15: ADC2 IN8
 77
 78required:
 79  - compatible
 80  - reg
 81  - clocks
 82  - clock-names
 83  - power-domains
 84  - '#io-channel-cells'
 85
 86# At least one of avvd/vref supplies
 87anyOf:
 88  - required:
 89      - adc1-vref-supply
 90      - adc1-avdd-supply
 91  - required:
 92      - adc2-vref-supply
 93      - adc2-avdd-supply
 94
 95additionalProperties: false
 96
 97examples:
 98  - |
 99    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
100
101    adc: adc@40065000 {
102      compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
103      reg = <0x40065000 0x200>;
104      clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
105      clock-names = "pclk", "adc";
106      power-domains = <&sysctrl>;
107      adc1-avdd-supply = <&adc1_avdd>;
108      adc1-vref-supply = <&adc1_vref>;
109      #io-channel-cells = <1>;
110    };
111...