snps,designware-i2c.yaml

  1# SPDX-License-Identifier: GPL-2.0-only
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Synopsys DesignWare APB I2C Controller
  8
  9maintainers:
 10  - Jarkko Nikula <jarkko.nikula@linux.intel.com>
 11
 12allOf:
 13  - $ref: /schemas/i2c/i2c-controller.yaml#
 14  - if:
 15      properties:
 16        compatible:
 17          not:
 18            contains:
 19              const: mscc,ocelot-i2c
 20    then:
 21      properties:
 22        reg:
 23          maxItems: 1
 24
 25properties:
 26  compatible:
 27    oneOf:
 28      - description: Generic Synopsys DesignWare I2C controller
 29        const: snps,designware-i2c
 30      - description: Renesas RZ/N1D I2C controller
 31        items:
 32          - const: renesas,r9a06g032-i2c  # RZ/N1D
 33          - const: renesas,rzn1-i2c       # RZ/N1
 34          - const: snps,designware-i2c
 35      - description: Baikal-T1 SoC System I2C controller
 36        const: baikal,bt1-sys-i2c
 37      - description: Mobileye EyeQ DesignWare I2C controller
 38        items:
 39          - enum:
 40              - mobileye,eyeq7h-i2c
 41          - const: mobileye,eyeq6lplus-i2c
 42          - const: snps,designware-i2c
 43      - items:
 44          - enum:
 45              - mobileye,eyeq6lplus-i2c
 46              - mscc,ocelot-i2c
 47              - sophgo,sg2044-i2c
 48              - thead,th1520-i2c
 49          - const: snps,designware-i2c
 50
 51  reg:
 52    minItems: 1
 53    items:
 54      - description: DW APB I2C controller memory mapped registers
 55      - description: |
 56          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
 57          This registers are specific to the Ocelot I2C-controller.
 58
 59  interrupts:
 60    maxItems: 1
 61
 62  clocks:
 63    minItems: 1
 64    items:
 65      - description: I2C controller reference clock source
 66      - description: APB interface clock source
 67
 68  clock-names:
 69    minItems: 1
 70    items:
 71      - const: ref
 72      - const: pclk
 73
 74  resets:
 75    maxItems: 1
 76
 77  clock-frequency:
 78    description: Desired I2C bus clock frequency in Hz
 79    enum: [100000, 400000, 1000000, 3400000]
 80    default: 400000
 81
 82  i2c-sda-hold-time-ns:
 83    description: |
 84      The property should contain the SDA hold time in nanoseconds. This option
 85      is only supported in hardware blocks version 1.11a or newer or on
 86      Microsemi SoCs.
 87
 88  i2c-scl-falling-time-ns:
 89    description: |
 90      The property should contain the SCL falling time in nanoseconds.
 91      This value is used to compute the tLOW period.
 92    default: 300
 93
 94  i2c-sda-falling-time-ns:
 95    description: |
 96      The property should contain the SDA falling time in nanoseconds.
 97      This value is used to compute the tHIGH period.
 98    default: 300
 99
100  dmas:
101    items:
102      - description: TX DMA Channel
103      - description: RX DMA Channel
104
105  dma-names:
106    items:
107      - const: tx
108      - const: rx
109
110  snps,bus-capacitance-pf:
111    $ref: /schemas/types.yaml#/definitions/uint32
112    description:
113      This property indicates the bus capacitance in picofarads (pF).
114      This value is used to compute the tHIGH and tLOW periods for high speed
115      mode.
116    enum: [100, 400]
117    default: 100
118
119  snps,clk-freq-optimized:
120    description:
121      This property indicates whether the hardware reduce its clock frequency
122      by reducing the internal latency required to generate the high period and
123      low period of SCL line.
124    type: boolean
125
126unevaluatedProperties: false
127
128required:
129  - compatible
130  - reg
131  - interrupts
132
133examples:
134  - |
135    i2c@f0000 {
136      compatible = "snps,designware-i2c";
137      reg = <0xf0000 0x1000>;
138      interrupts = <11>;
139      clock-frequency = <400000>;
140    };
141  - |
142    i2c@1120000 {
143      compatible = "snps,designware-i2c";
144      reg = <0x1120000 0x1000>;
145      interrupts = <12 1>;
146      clock-frequency = <400000>;
147      i2c-sda-hold-time-ns = <300>;
148      i2c-sda-falling-time-ns = <300>;
149      i2c-scl-falling-time-ns = <300>;
150      snps,bus-capacitance-pf = <400>;
151      snps,clk-freq-optimized;
152    };
153  - |
154    i2c@2000 {
155      compatible = "snps,designware-i2c";
156      reg = <0x2000 0x100>;
157      #address-cells = <1>;
158      #size-cells = <0>;
159      clock-frequency = <400000>;
160      clocks = <&i2cclk>;
161      interrupts = <0>;
162
163      eeprom@64 {
164        compatible = "atmel,24c02";
165        reg = <0x64>;
166      };
167    };
168  - |
169    i2c@100400 {
170      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
171      reg = <0x100400 0x100>, <0x198 0x8>;
172      pinctrl-0 = <&i2c_pins>;
173      pinctrl-names = "default";
174      interrupts = <8>;
175      clocks = <&ahb_clk>;
176    };
177...