i2c-altera.txt

 1* Altera I2C Controller
 2* This is Altera's synthesizable logic block I2C Controller for use
 3* in Altera's FPGAs.
 4
 5Required properties :
 6 - compatible : should be "altr,softip-i2c-v1.0"
 7 - reg        : Offset and length of the register set for the device
 8 - interrupts : <IRQ> where IRQ is the interrupt number.
 9 - clocks     : phandle to input clock.
10 - #address-cells = <1>;
11 - #size-cells = <0>;
12
13Recommended properties :
14 - clock-frequency : desired I2C bus clock frequency in Hz.
15
16Optional properties :
17 - fifo-size : Size of the RX and TX FIFOs in bytes.
18 - Child nodes conforming to i2c bus binding
19
20Example :
21
22	i2c@100080000 {
23		compatible = "altr,softip-i2c-v1.0";
24		reg = <0x00000001 0x00080000 0x00000040>;
25		interrupt-parent = <&intc>;
26		interrupts = <0 43 4>;
27		clocks = <&clk_0>;
28		clock-frequency = <100000>;
29		#address-cells = <1>;
30		#size-cells = <0>;
31		fifo-size = <4>;
32
33		eeprom@51 {
34			compatible = "atmel,24c32";
35			reg = <0x51>;
36			pagesize = <32>;
37		};
38	};
39