nvidia,tegra210-nvdec.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra NVDEC
  8
  9description: |
 10  NVDEC is the hardware video decoder present on NVIDIA Tegra210
 11  and newer chips. It is located on the Host1x bus and typically
 12  programmed through Host1x channels.
 13
 14maintainers:
 15  - Thierry Reding <treding@gmail.com>
 16  - Mikko Perttunen <mperttunen@nvidia.com>
 17
 18properties:
 19  $nodename:
 20    pattern: "^nvdec@[0-9a-f]*$"
 21
 22  compatible:
 23    enum:
 24      - nvidia,tegra210-nvdec
 25      - nvidia,tegra186-nvdec
 26      - nvidia,tegra194-nvdec
 27
 28  reg:
 29    maxItems: 1
 30
 31  clocks:
 32    maxItems: 1
 33
 34  clock-names:
 35    items:
 36      - const: nvdec
 37
 38  resets:
 39    maxItems: 1
 40
 41  reset-names:
 42    items:
 43      - const: nvdec
 44
 45  power-domains:
 46    maxItems: 1
 47
 48  iommus:
 49    maxItems: 1
 50
 51  dma-coherent: true
 52
 53  interconnects:
 54    items:
 55      - description: DMA read memory client
 56      - description: DMA read 2 memory client
 57      - description: DMA write memory client
 58
 59  interconnect-names:
 60    items:
 61      - const: dma-mem
 62      - const: read-1
 63      - const: write
 64
 65  nvidia,host1x-class:
 66    description: |
 67      Host1x class of the engine, used to specify the targeted engine
 68      when programming the engine through Host1x channels or when
 69      configuring engine-specific behavior in Host1x.
 70    default: 0xf0
 71    $ref: /schemas/types.yaml#/definitions/uint32
 72
 73required:
 74  - compatible
 75  - reg
 76  - clocks
 77  - clock-names
 78  - resets
 79  - reset-names
 80  - power-domains
 81
 82additionalProperties: false
 83
 84examples:
 85  - |
 86    #include <dt-bindings/clock/tegra186-clock.h>
 87    #include <dt-bindings/interrupt-controller/arm-gic.h>
 88    #include <dt-bindings/memory/tegra186-mc.h>
 89    #include <dt-bindings/power/tegra186-powergate.h>
 90    #include <dt-bindings/reset/tegra186-reset.h>
 91
 92    nvdec@15480000 {
 93            compatible = "nvidia,tegra186-nvdec";
 94            reg = <0x15480000 0x40000>;
 95            clocks = <&bpmp TEGRA186_CLK_NVDEC>;
 96            clock-names = "nvdec";
 97            resets = <&bpmp TEGRA186_RESET_NVDEC>;
 98            reset-names = "nvdec";
 99
100            power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
101            interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
102                            <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
103                            <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
104            interconnect-names = "dma-mem", "read-1", "write";
105            iommus = <&smmu TEGRA186_SID_NVDEC>;
106    };