gpio-mvebu.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Marvell EBU GPIO controller
  8
  9maintainers:
 10  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 11  - Andrew Lunn <andrew@lunn.ch>
 12
 13properties:
 14  compatible:
 15    oneOf:
 16      - enum:
 17          - marvell,armada-8k-gpio
 18          - marvell,orion-gpio
 19
 20      - items:
 21          - enum:
 22              - marvell,mv78200-gpio
 23              - marvell,armada-370-gpio
 24          - const: marvell,orion-gpio
 25
 26      - description: Deprecated binding
 27        items:
 28          - const: marvell,armadaxp-gpio
 29          - const: marvell,orion-gpio
 30        deprecated: true
 31
 32  reg:
 33    description: |
 34      Address and length of the register set for the device. Not used for
 35      marvell,armada-8k-gpio.
 36
 37      A second entry can be provided, for the PWM function using the GPIO Blink
 38      Counter on/off registers.
 39    minItems: 1
 40    maxItems: 2
 41
 42  reg-names:
 43    items:
 44      - const: gpio
 45      - const: pwm
 46    minItems: 1
 47
 48  offset:
 49    $ref: /schemas/types.yaml#/definitions/uint32
 50    description: Offset in the register map for the gpio registers (in bytes)
 51
 52  interrupts:
 53    description: |
 54      The list of interrupts that are used for all the pins managed by this
 55      GPIO bank. There can be more than one interrupt (example: 1 interrupt
 56      per 8 pins on Armada XP, which means 4 interrupts per bank of 32
 57      GPIOs).
 58    minItems: 1
 59    maxItems: 4
 60
 61  interrupt-controller: true
 62
 63  "#interrupt-cells":
 64    const: 2
 65
 66  gpio-controller: true
 67
 68  ngpios:
 69    minimum: 1
 70    maximum: 32
 71
 72  "#gpio-cells":
 73    const: 2
 74
 75  gpio-ranges:
 76    maxItems: 1
 77
 78  marvell,pwm-offset:
 79    $ref: /schemas/types.yaml#/definitions/uint32
 80    description: Offset in the register map for the pwm registers (in bytes)
 81
 82  "#pwm-cells":
 83    description:
 84      The first cell is the GPIO line number. The second cell is the period
 85      in nanoseconds.
 86    const: 2
 87
 88  clocks:
 89    description:
 90      Clock(s) used for PWM function.
 91    items:
 92      - description: Core clock
 93      - description: AXI bus clock
 94    minItems: 1
 95
 96  clock-names:
 97    items:
 98      - const: core
 99      - const: axi
100    minItems: 1
101
102patternProperties:
103  "^(.+-hog(-[0-9]+)?)$":
104    type: object
105
106    required:
107      - gpio-hog
108
109required:
110  - compatible
111  - gpio-controller
112  - ngpios
113  - "#gpio-cells"
114
115allOf:
116  - if:
117      properties:
118        compatible:
119          contains:
120            const: marvell,armada-8k-gpio
121    then:
122      required:
123        - offset
124    else:
125      required:
126        - reg
127
128unevaluatedProperties: false
129
130examples:
131  - |
132    gpio@d0018100 {
133      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
134      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
135      ngpios = <32>;
136      gpio-controller;
137      #gpio-cells = <2>;
138      interrupt-controller;
139      #interrupt-cells = <2>;
140      interrupts = <16>, <17>, <18>, <19>;
141    };
142
143  - |
144    gpio@18140 {
145      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
146      reg = <0x18140 0x40>, <0x181c8 0x08>;
147      reg-names = "gpio", "pwm";
148      ngpios = <17>;
149      gpio-controller;
150      #gpio-cells = <2>;
151      #pwm-cells = <2>;
152      interrupt-controller;
153      #interrupt-cells = <2>;
154      interrupts = <87>, <88>, <89>;
155      clocks = <&coreclk 0>;
156    };