gpio-mmio.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Generic MMIO GPIO
  8
  9maintainers:
 10  - Linus Walleij <linusw@kernel.org>
 11  - Bartosz Golaszewski <brgl@bgdev.pl>
 12
 13description:
 14  Some simple GPIO controllers may consist of a single data register or a pair
 15  of set/clear-bit registers. Such controllers are common for glue logic in
 16  FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
 17  NAND-style parallel busses.
 18
 19properties:
 20  compatible:
 21    enum:
 22      - brcm,bcm6345-gpio
 23      - ni,169445-nand-gpio
 24      - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
 25      - intel,ixp4xx-expansion-bus-mmio-gpio
 26
 27  big-endian: true
 28
 29  '#gpio-cells':
 30    const: 2
 31
 32  gpio-controller: true
 33
 34  little-endian: true
 35
 36  reg:
 37    minItems: 1
 38    description:
 39      A list of registers in the controller. The width of each register is
 40      determined by its size. All registers must have the same width. The number
 41      of GPIOs is set by the width, with bit 0 corresponding to GPIO 0, unless
 42      the ngpios property further restricts the number of used lines.
 43    items:
 44      - description:
 45          Register to READ the value of the GPIO lines. If GPIO line is high,
 46          the bit will be set. If the GPIO line is low, the bit will be cleared.
 47          This register may also be used to drive GPIOs if the SET register is
 48          omitted.
 49      - description:
 50          Register to SET the value of the GPIO lines. Setting a bit in this
 51          register will drive the GPIO line high.
 52      - description:
 53          Register to CLEAR the value of the GPIO lines. Setting a bit in this
 54          register will drive the GPIO line low. If this register is omitted,
 55          the SET register will be used to clear the GPIO lines as well, by
 56          actively writing the line with 0.
 57      - description:
 58          Register to set the line as OUTPUT. Setting a bit in this register
 59          will turn that line into an output line. Conversely, clearing a bit
 60          will turn that line into an input.
 61      - description:
 62          Register to set this line as INPUT. Setting a bit in this register
 63          will turn that line into an input line. Conversely, clearing a bit
 64          will turn that line into an output.
 65
 66  reg-names:
 67    minItems: 1
 68    maxItems: 5
 69    items:
 70      enum:
 71        - dat
 72        - set
 73        - clr
 74        - dirout
 75        - dirin
 76
 77  native-endian: true
 78
 79  ngpios:
 80    minimum: 1
 81    maximum: 63
 82    description:
 83      If this property is present the number of usable GPIO lines are restricted
 84      to the first 0 .. ngpios lines. This is useful when the GPIO MMIO register
 85      has 32 bits for GPIO but only the first 12 are actually connected to
 86      real electronics, and then we set ngpios to 12.
 87
 88  no-output:
 89    $ref: /schemas/types.yaml#/definitions/flag
 90    description:
 91      If this property is present, the controller cannot drive the GPIO lines.
 92
 93if:
 94  properties:
 95    compatible:
 96      contains:
 97        const: intel,ixp4xx-expansion-bus-mmio-gpio
 98then:
 99  $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
100
101patternProperties:
102  "^.+-hog(-[0-9]+)?$":
103    type: object
104    required:
105      - gpio-hog
106
107required:
108  - compatible
109  - reg
110  - reg-names
111  - '#gpio-cells'
112  - gpio-controller
113
114unevaluatedProperties: false
115
116examples:
117  - |
118    gpio@1f300010 {
119      compatible = "ni,169445-nand-gpio";
120      reg = <0x1f300010 0x4>;
121      reg-names = "dat";
122      gpio-controller;
123      #gpio-cells = <2>;
124    };
125
126    gpio@e0100000 {
127      compatible = "wd,mbl-gpio";
128      reg-names = "dat";
129      reg = <0xe0100000 0x1>;
130      #gpio-cells = <2>;
131      gpio-controller;
132      no-output;
133    };
134
135    gpio@fffe0406 {
136      compatible = "brcm,bcm6345-gpio";
137      reg-names = "dirout", "dat";
138      reg = <0xfffe0406 2>, <0xfffe040a 2>;
139      ngpios = <15>;
140      native-endian;
141      gpio-controller;
142      #gpio-cells = <2>;
143    };
144
145    bus@c4000000 {
146        compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
147        reg = <0xc4000000 0x30>;
148        native-endian;
149        #address-cells = <2>;
150        #size-cells = <1>;
151        ranges = <0 0x0 0x50000000 0x01000000>;
152        dma-ranges = <0 0x0 0x50000000 0x01000000>;
153        gpio@1,0 {
154            compatible = "intel,ixp4xx-expansion-bus-mmio-gpio";
155            gpio-controller;
156            #gpio-cells = <2>;
157            big-endian;
158            reg = <1 0x00000000 0x2>;
159            reg-names = "dat";
160            intel,ixp4xx-eb-write-enable = <1>;
161        };
162    };