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fairchild,74hc595.yaml

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linux-6.19.14/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml YAML
 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Generic 8-bit shift register
 8
 9description: |
10  NOTE: These chips nominally don't have a chip select pin. They do however
11  have a rising-edge triggered latch clock (or storage register clock) pin,
12  which behaves like an active-low chip select.
13
14  After the bits are shifted into the shift register, CS# is driven high, which
15  the 74HC595 sees as a rising edge on the latch clock that results in a
16  transfer of the bits from the shift register to the storage register and thus
17  to the output pins.
18                      _   _       _   _
19  shift clock    ____| |_| |_..._| |_| |_________
20
21  latch clock                           * trigger
22                 ___                     ________
23  chip select#      |___________________|
24
25maintainers:
26  - Maxime Ripard <mripard@kernel.org>
27
28properties:
29  compatible:
30    enum:
31      - fairchild,74hc595
32      - nxp,74lvc594
33
34  reg:
35    maxItems: 1
36
37  gpio-controller: true
38
39  '#gpio-cells':
40    description:
41      The second cell is only used to specify the GPIO polarity.
42    const: 2
43
44  registers-number:
45    $ref: /schemas/types.yaml#/definitions/uint32
46    description: Number of daisy-chained shift registers
47
48  enable-gpios:
49    description: GPIO connected to the OE (Output Enable) pin.
50    maxItems: 1
51
52patternProperties:
53  "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
54    type: object
55    required:
56      - gpio-hog
57
58required:
59  - compatible
60  - reg
61  - gpio-controller
62  - '#gpio-cells'
63  - registers-number
64
65allOf:
66  - $ref: /schemas/spi/spi-peripheral-props.yaml#
67
68unevaluatedProperties: false
69
70examples:
71  - |
72    spi {
73        #address-cells = <1>;
74        #size-cells = <0>;
75
76        gpio5@0 {
77            compatible = "fairchild,74hc595";
78            reg = <0>;
79            gpio-controller;
80            #gpio-cells = <2>;
81            registers-number = <4>;
82            spi-max-frequency = <100000>;
83        };
84    };
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