nvidia,tegra186-bpmp.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
  8
  9maintainers:
 10  - Thierry Reding <thierry.reding@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12
 13description: |
 14  The BPMP is a specific processor in Tegra chip, which is designed for
 15  booting process handling and offloading the power management, clock
 16  management, and reset control tasks from the CPU. The binding document
 17  defines the resources that would be used by the BPMP firmware driver,
 18  which can create the interprocessor communication (IPC) between the
 19  CPU and BPMP.
 20
 21  This node is a mailbox consumer. See the following files for details
 22  of the mailbox subsystem, and the specifiers implemented by the
 23  relevant provider(s):
 24
 25    - .../mailbox/mailbox.txt
 26    - .../mailbox/nvidia,tegra186-hsp.yaml
 27
 28  This node is a clock, power domain, and reset provider. See the
 29  following files for general documentation of those features, and the
 30  specifiers implemented by this node:
 31
 32    - .../clock/clock-bindings.txt
 33    - <dt-bindings/clock/tegra186-clock.h>
 34    - ../power/power-domain.yaml
 35    - <dt-bindings/power/tegra186-powergate.h>
 36    - .../reset/reset.txt
 37    - <dt-bindings/reset/tegra186-reset.h>
 38
 39  The BPMP implements some services which must be represented by
 40  separate nodes. For example, it can provide access to certain I2C
 41  controllers, and the I2C bindings represent each I2C controller as a
 42  device tree node. Such nodes should be nested directly inside the main
 43  BPMP node.
 44
 45  Software can determine whether a child node of the BPMP node
 46  represents a device by checking for a compatible property. Any node
 47  with a compatible property represents a device that can be
 48  instantiated. Nodes without a compatible property may be used to
 49  provide configuration information regarding the BPMP itself, although
 50  no such configuration nodes are currently defined by this binding.
 51
 52  The BPMP firmware defines no single global name-/numbering-space for
 53  such services. Put another way, the numbering scheme for I2C buses is
 54  distinct from the numbering scheme for any other service the BPMP may
 55  provide (e.g. a future hypothetical SPI bus service). As such, child
 56  device nodes will have no reg property, and the BPMP node will have no
 57  "#address-cells" or "#size-cells" property.
 58
 59  The shared memory area for the IPC TX and RX between CPU and BPMP are
 60  predefined and work on top of either sysram, which is an SRAM inside the
 61  chip, or in normal SDRAM.
 62  See ".../sram/sram.yaml" for the bindings for the SRAM case.
 63  See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
 64  the SDRAM case.
 65
 66properties:
 67  compatible:
 68    oneOf:
 69      - items:
 70          - enum:
 71              - nvidia,tegra194-bpmp
 72              - nvidia,tegra234-bpmp
 73              - nvidia,tegra264-bpmp
 74          - const: nvidia,tegra186-bpmp
 75      - const: nvidia,tegra186-bpmp
 76
 77  mboxes:
 78    description: A phandle and channel specifier for the mailbox used to
 79      communicate with the BPMP.
 80    maxItems: 1
 81
 82  shmem:
 83    description: List of the phandle to the TX and RX shared memory area
 84      that the IPC between CPU and BPMP is based on.
 85    minItems: 2
 86    maxItems: 2
 87
 88  memory-region:
 89    description: phandle to reserved memory region used for IPC between
 90      CPU-NS and BPMP.
 91    maxItems: 1
 92
 93  "#clock-cells":
 94    const: 1
 95
 96  "#power-domain-cells":
 97    const: 1
 98
 99  "#reset-cells":
100    const: 1
101
102  interconnects:
103    items:
104      - description: memory read client
105      - description: memory write client
106      - description: DMA read client
107      - description: DMA write client
108
109  interconnect-names:
110    items:
111      - const: read
112      - const: write
113      - const: dma-mem # dma-read
114      - const: dma-write
115
116  iommus:
117    maxItems: 1
118
119  i2c:
120    type: object
121
122  thermal:
123    type: object
124
125additionalProperties: false
126
127oneOf:
128  - required:
129      - memory-region
130  - required:
131      - shmem
132
133required:
134  - compatible
135  - mboxes
136  - "#clock-cells"
137  - "#power-domain-cells"
138  - "#reset-cells"
139
140examples:
141  - |
142    #include <dt-bindings/interrupt-controller/arm-gic.h>
143    #include <dt-bindings/mailbox/tegra186-hsp.h>
144    #include <dt-bindings/memory/tegra186-mc.h>
145
146    hsp_top0: hsp@3c00000 {
147        compatible = "nvidia,tegra186-hsp";
148        reg = <0x03c00000 0xa0000>;
149        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
150        interrupt-names = "doorbell";
151        #mbox-cells = <2>;
152    };
153
154    sram@30000000 {
155        compatible = "nvidia,tegra186-sysram", "mmio-sram";
156        reg = <0x30000000 0x50000>;
157        #address-cells = <1>;
158        #size-cells = <1>;
159        ranges = <0x0 0x30000000 0x50000>;
160
161        cpu_bpmp_tx: sram@4e000 {
162            reg = <0x4e000 0x1000>;
163            label = "cpu-bpmp-tx";
164            pool;
165        };
166
167        cpu_bpmp_rx: sram@4f000 {
168            reg = <0x4f000 0x1000>;
169            label = "cpu-bpmp-rx";
170            pool;
171        };
172    };
173
174    bpmp {
175        compatible = "nvidia,tegra186-bpmp";
176        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
177                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
178                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
179                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
180        interconnect-names = "read", "write", "dma-mem", "dma-write";
181        iommus = <&smmu TEGRA186_SID_BPMP>;
182        mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
183        shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
184        #clock-cells = <1>;
185        #power-domain-cells = <1>;
186        #reset-cells = <1>;
187
188        i2c {
189            compatible = "nvidia,tegra186-bpmp-i2c";
190            nvidia,bpmp-bus-id = <5>;
191            #address-cells = <1>;
192            #size-cells = <0>;
193        };
194
195        thermal {
196            compatible = "nvidia,tegra186-bpmp-thermal";
197            #thermal-sensor-cells = <1>;
198        };
199    };
200
201  - |
202    #include <dt-bindings/mailbox/tegra186-hsp.h>
203
204    bpmp {
205        compatible = "nvidia,tegra186-bpmp";
206        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
207                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
208                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
209                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
210        interconnect-names = "read", "write", "dma-mem", "dma-write";
211        mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
212        memory-region = <&dram_cpu_bpmp_mail>;
213        #clock-cells = <1>;
214        #power-domain-cells = <1>;
215        #reset-cells = <1>;
216    };